Electron and hole mobility in silicon at large operating temperatures. I. Bulk mobility

Reggiani, Susanna; Valdinoci, M.; Colalongo, L.; Rudan, Massimo; Baccarani, G.; Stricker, Andy; Illien, F.; Felber, N.; Fichtner, W.; Zullino, L.

doi:10.1109/16.987121

Cited by 116 publications

(54 citation statements)

References 13 publications

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“…Our experiment in [21] is also reporting a similar c value for the GAA triangular Si nanowires with a slightly bigger cross-section (sub-20 nm) with the same doping level. All the three studies in [20][21][22] are in line with the previous reports for intrinsic or low-doped Si [23] being explained by the dominant role of ionized impurity scattering in highly doped Si MOSFETs, even for the deeply scaled Si nanowires.…”

Section: Scattering Mechanism In Deeply Scaled Highly Doped Si Nanowiressupporting

confidence: 77%

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

Najmzadeh¹,

Bouvet²,

Grabinski³

et al. 2012

Solid-State Electronics

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a b s t r a c tIn this work we report dense arrays of accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-sections in a highly doped regime. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve P2.5 GPa uniaxial tensile stress in the Si nanowire is reported. The deeply scaled Si nanowire including such uniaxial tensile stress shows a low-field electron mobility of 332 cm 2 /V s at room temperature, 32% higher than bulk mobility at the equivalent high channel doping. The conduction mechanism as well as high temperature performance was studied based on the electrical characteristics from room temperature up to %400 K and a V TH drift of À1.72 mV/K and an ionized impurity scattering-based mobility reduction were observed.

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Section: Scattering Mechanism In Deeply Scaled Highly Doped Si Nanowiressupporting

confidence: 77%

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

Najmzadeh¹,

Bouvet²,

Grabinski³

et al. 2012

Solid-State Electronics

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“…For low temperatures, Klaassen's model seems to overestimate the mobility sum. Discrepancies between Klaassen's model and experimental data have been observed before at low (<200 K) or high (>400 K) temperatures [20]. However, the validity of Klaassen's model when both injection and temperature vary has not been assessed before.…”

Section: Measuring the Influence Of Temperaturementioning

confidence: 93%

A Contactless Method for Determining the Carrier Mobility Sum in Silicon Wafers

Rougieux

Zheng

Thiboust

et al. 2012

IEEE J. Photovoltaics

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Abstract-In this paper, we present a new method to determine the simultaneous injection and temperature dependence of the sum of the majority and minority carrier mobilities in silicon wafers. The technique is based on combining transient and quasi-steadystate photoconductance measurements. It does not require a full device structure or contacting but only adequate surface passivation. The mobility dependence on both carrier injection level and temperature, as measured on several test samples, is discussed and compared with well-known mobility models. The potential of this method to measure the impact of dopant concentration, compensation ratio, injection level, and temperature on the mobility is demonstrated.

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“…Since we perform a 2D simulation, an area factor equal to 1µm was used as transistor width. For mobility models, we have used the Philips unified model [7,9] together with the Lombardi's model for thin layers [7,10,11]. Finally, quantum corrections are taken in to account in these simulations [7].…”

Section: Methodsmentioning

confidence: 99%

Simulación TCAD para un MOSFET de silicio en aislante, ultra fino con óxido enterrado y completamente agotado: una comparación entre COMSOL y Sentaurus

Prócel

Trojman

2014

Av. Cienc. Ing. (Quito)

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ARTÍCULO/ARTICLE SECCIÓN/SECTION C EN CIENCIAS E INGENIERÍAS AVANCES TCAD Simulation for ultrathin body and buried oxide fully depleted silicon-on-insulatorMOSFET: a comparison between COMSOL and Sentaurus Simulación TCAD para un MOSFET de silicio en aislante, ultra fino con óxido enterrado y completamente agotado: una comparación entre COMSOL y Sentaurus AbstractIn the present work, we develop a model for simulating an ultrathin body (10nm) and buried oxide (20nm) fully-depleted silicon-on-insulator MOSFET with SiO2 gate oxide (5nm) by using TCAD-Sentaurus software. We performed DC-simulations for studying the behavior of the threshold voltage and the transconductance. Furthermore, AC-simulations were performed for studying the inversion capacitance and the inversion charge. We compare our results with similar simulations carried out in a previous work in which COMSOLMultiphysics software was used. We have obtained similar results in both works. However, Sentaurus features more interesting details like introducing a more realistic picture of the physical mechanisms of such complex devices. Keywords. SOI-MOSFET, TCAD-simulation, Sentaurus, Poisson's equation, driftdiffusion equations. ResumenEn el presente trabajo, se desarrolla un modelo para simular un dispositivo MOSFET de silicio en aislante, ultra delgados con oxido enterrado (20m) y agotados completamente con SiO2 (5nm) como compuerta. El software que se usa es TCAD-Sentaurus. Se desarrollaron simulaciones DC para estudiar el comportamiento del voltaje de encendido y la transconductancia. Además, se desarrollaron simulaciones AC para estudiar la capacitancia y carga de inversión. Los resultados fueron comparados con un trabajo previo en el que se usó como simulador al programa COMSOL-Multiphysics. Los resultados obtenidos son muy similares entre ambos trabajos. Sin embargo, Sentaurus ofrece características más interesantes como introducir modelos más reales para los mecanismos físicos de dispositivos complejos.Palabras Clave. SOI-MOSFET, simulación TCAD, Sentaurus, ecuación de Poisson, ecuaciones de difusión y deriva.

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Electron and hole mobility in silicon at large operating temperatures. I. Bulk mobility

Cited by 116 publications

References 13 publications

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

A Contactless Method for Determining the Carrier Mobility Sum in Silicon Wafers

Simulación TCAD para un MOSFET de silicio en aislante, ultra fino con óxido enterrado y completamente agotado: una comparación entre COMSOL y Sentaurus

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