Electromigration failure mechanism studies on copper interconnects

Abstract

Electromigration (EM) studies revealed a strong correlation between observed failure scenario and local microstructural properties at the via-to-line-transition, in particular that of the liner. "Early" failure modes were found to have not only smaller failure times but also a lower current density exponent. The influence of specific processes on the occurrence ofcertain failure modes will he discussed. IntroductionThe EM resistivity of bulk copper is known to be larger compared to AI(Cu) [I]. However, failure times measured on integrated Cu interconnects strongly depend on the used integration scheme and the degree of process control. The presence of "early" failure modes can result in a reduction of EM lifetimes to a level similar to AI(Cu) or even below. Ofien, two or more different physical failure mechanisms act in parallel within a test sample or a single interconnect.

Cathode edge displacement by voiding coupled with grain boundary grooving in bamboo like metallic interconnects by surface drift-diffusion under the capillary and electromigration forces

“…(17) may be very limited if one uses the Damascene configuration where the electric contacts are established at the lower surfaces of the anode and cathode edges of the interconnects lines having top surface acting as dominant diffusion path because of no capping (trenchvoiding), as it was the case of Hu et al (1997) and Fischer et al (2002). Then, Eq.…”

“…This opposes our presumption that the electrical contact to the specimen is established at the cathode edge by the DMCE without soldering. However, this concept of CCFT by voiding still may be applied to Cu-Damascene interconnect line under very special conditions, namely; the via regions are the natural extension of the test specimen similar to Cu-via and the surface is capped with metal coating (CoWP, CoSnP, or Pd) to inhibit SN x coated top interface from acting as a fast drift-diffusion path (Hu et al, 2002(Hu et al, , 2004Fischer et al, 2002). According to experimental findings, (Hu et al, 2002), mostly the via-bottom void is observed in the capped samples, which is a strong indication that the sidewall and via-bottom interfaces may play dominate diffusion paths rather than the top surface or interfacial layer.…”

“…Furthermore, this also shows that not the cathode edge displacement but the via contact area shrinkage by voiding (via-voiding) is the primary cause for the electrical break down. Then, CCRT concept mentioned above may be employed for the prediction of the cathode failure time by careful evaluation of the effective path lengthŵ, which may be replaced by the dimension of the via parallel to the longitudinal direction of the line, especially in those cases where the interfacial layer between Cu-via and the under liner W-Mo or Cu interconnect line C and W-via shows rather poor adhesion (wetting) properties (Fischer et al, 2002).…”

Dynamic void formation in a DD-copper-structure with different metallization geometry

“…All structures were investigated under normally chosen test conditions [1,2,8]. The applied current density was varied between 0.3 MA/ cm 2 and 25 MA/cm 2 .…”

“…A calculation routine based on FORTRAN is used for the determination of the local mass flux divergences and the dynamic void formation in the model. First the suitability of the simulation and calculations will be shown by the determination of the void formation for a copper interconnect structure taken from the literature [2]. For comparison of the different influences default models were created.…”