2013 IEEE International Reliability Physics Symposium (IRPS) 2013
DOI: 10.1109/irps.2013.6531951
|View full text |Cite
|
Sign up to set email alerts
|

Electromigration early failure void nucleation and growth phenomena in Cu and Cu(Mn) interconnects

Abstract: Electromigration early failure void nucleation and growth phenomena were studied using large-scale, statistical analysis methods. A total of about 496,000 interconnects were tested over a wide current density and temperature range (j = 3.4 to 41.2 µmA/m2, T = 200 to 350°C) to analyze the detailed behavior of the current density exponent n and the activation energy Ea. The results for the critical V1M1 downstream interface indicate a reduction from n = 1.55±0.10 to n = 1.15±0.15 when lowering the temperature to… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
4
1

Citation Types

2
12
0

Year Published

2015
2015
2021
2021

Publication Types

Select...
3
2
1

Relationship

0
6

Authors

Journals

citations
Cited by 39 publications
(14 citation statements)
references
References 8 publications
2
12
0
Order By: Relevance
“…Applications targeted for di erent use cases face di erent environmental conditions and quality goals. Among others, the JEDEC Solid State Technology Association (JEDEC) [13] and the Automotive Electronics Council (AEC) [2] released several standards on (1) how to characterize and to qualify a semiconductor technology with respect to intrinsic and extrinsic failure mechanisms and (2) how to scale technology and design parameters for speci c use cases. With respect to EM, these standards include JEP001A, JEP119A, JEP122H, JESD63, JESD87, JESD202 and AECQ-100.…”
Section: Em-aware Layout Design and Mission Profiles In Industrial Prmentioning
confidence: 99%
See 4 more Smart Citations
“…Applications targeted for di erent use cases face di erent environmental conditions and quality goals. Among others, the JEDEC Solid State Technology Association (JEDEC) [13] and the Automotive Electronics Council (AEC) [2] released several standards on (1) how to characterize and to qualify a semiconductor technology with respect to intrinsic and extrinsic failure mechanisms and (2) how to scale technology and design parameters for speci c use cases. With respect to EM, these standards include JEP001A, JEP119A, JEP122H, JESD63, JESD87, JESD202 and AECQ-100.…”
Section: Em-aware Layout Design and Mission Profiles In Industrial Prmentioning
confidence: 99%
“…The derivation of the parameters of the EM-failure model during technology characterization is done under temperature-accelerated conditions (JESD63, JESD202 [13]). Next, the current density j char used during the characterization of a particular layer and temperature T char must be scaled (using Black's Equation [6]) to one or more technology-speci c reference conditions j max,ref at T ref while considering reliability goals (Fig.…”
Section: Design Technologymentioning
confidence: 99%
See 3 more Smart Citations