2010
DOI: 10.1016/j.elecom.2010.03.028
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Electrochemical etching process to tune the diameter of arrayed deep pores by controlling carrier collection at a semiconductor–electrolyte interface

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Cited by 6 publications
(4 citation statements)
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“…When the silicon is immersed into an electrolyte, a spacecharge region (SCR) is present in the semiconductor electrode and serves as a Schottky barrier. 25,26 The width of the SCR depends on the built-in potential V bi , on the p-type doping density, on the applied bias V appl , and on the interface geometry and becomes thin at the sharp edges (i.e. etch pit or pore tip) comparing with the other flat areas.…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…When the silicon is immersed into an electrolyte, a spacecharge region (SCR) is present in the semiconductor electrode and serves as a Schottky barrier. 25,26 The width of the SCR depends on the built-in potential V bi , on the p-type doping density, on the applied bias V appl , and on the interface geometry and becomes thin at the sharp edges (i.e. etch pit or pore tip) comparing with the other flat areas.…”
Section: Resultsmentioning
confidence: 99%
“…etch pit or pore tip) comparing with the other flat areas. 25,26 However, the barrier height (E b ) is independent of geometry and is estimated from the following equation 1: 25 E b = e(V bi − V appl ) − 2kT [ 1 ] where V bi is the built-in potential, V appl is the applied bias, k is the Boltzmann constant, e is the elementary charge, and T is the temperature. Thus, we investigated the rectifying characteristics of the electrolyte/silicon wire (length 13 μm)/p-silicon substrate/Al structure used normally in our experiment, resulting in exhibiting a typical rectifying behavior as shown in Fig.…”
Section: Resultsmentioning
confidence: 99%
“…14(c). In addition, by decreasing the supply of holes to the reaction sites, the diameter of the pores could be tuned, 45 as is shown in Fig. 14(d).…”
Section: Fabrication Of High-aspect-ratio Arrayed Microstructuresmentioning
confidence: 98%
“…6 This technique has, however, mostly been studied for the fabrication of pore arrays in the micrometer range. [7][8][9] The current development of silicon nanodevices sometimes requires integrating pore arrays with higher densities. For instance, 500 nm pore arrays are necessary to confine light within the wavelength ranges applicable to telecommunications.…”
mentioning
confidence: 99%