Electrical, Thermal, and Mechanical Characterization of eWLB, Fully Molded Fan-Out Package, and Fan-Out Chip Last Package

Shih, Meng-Kai; Huang, Chun-Yueh; Chen, Tsan-Hsien; Wang, Chen-Chao; Tarng, David; Hung, Chih-Pin

doi:10.1109/tcpmt.2019.2935477

Cited by 24 publications

(5 citation statements)

References 18 publications

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“…To examine the thermal, mechanical and electrical response of the three Fan-out (FO) packaging technologies shown in Fig. 13, a 3D numerical model is proposed in [82]. The study confirmed that FOCLP has the highest warpage due to the CTE mismatch between the molding materials and the thin substrate.…”

Section: ) Modeling Of Wafer-level Packagingmentioning

confidence: 89%

A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges

et al. 2022

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We present in this paper design considerations and implementation challenges of a proposed versatile SoC/SiP sensor interface intended for industrial applications. The proposed interface involves high-voltage circuits such as class-D power amplifiers, gate drivers, level shifters, and electrical isolators. Also, it includes low-voltage blocks like programmable gain amplifiers and ADCs. In addition, DC-to-DC converters are used to supply the various building blocks of the projected sensor interface. The key challenges for implementing each block are discussed in this paper. Also, the technological aspects to support the proposed SoC/SiP solution are given. Moreover, the different available packaging technologies to implement the intended SiP solution are discussed in addition to the thermal aspects associated with the system packaging.INDEX TERMS Industrial applications, sensor interface, versatility, system-on-chip (SoC), system-inpackage (SiP), thermal management. Author et al.: Preparation of Papers for IEEE TRANSACTIONS and JOURNALS TABLE 1. Performance Comparison of High-Voltage and High-Power Class-D Power Amplifiers. YVES AUDET (Member, IEEE) received the B.Sc. degree and the M.Sc. degree in physics from the

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Section: ) Modeling Of Wafer-level Packagingmentioning

confidence: 89%

A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges

et al. 2022

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“…In this study, in addition to using the aforementioned EMC, the material properties of EMC were further modified to observe their effects on wafer warpage. Based on a literature review of EMC material parameters [1][2][3][4][5][6]8,15,16], the upper and lower limits of adjustable material values were summarized and organized as shown in Table 4. The range of modulation of Young's modulus was defined in the study as the temperature interval before and after the Tg point of the EMC, named the temperature interval E L (from 25 • C to 35 • C) and E H (from 235 • C to 260 • C), respectively, with ∆T as the temperature interval between E L and E H (as shown in Figure 7).…”

Section: Establishing Materials Parametersmentioning

confidence: 99%

Exploring the Influence of Material Properties of Epoxy Molding Compound on Wafer Warpage in Fan-Out Wafer-Level Packaging

2023

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This study investigated the impact of material properties of epoxy molding compounds on wafer warpage in fan-out wafer-level packaging. As there is currently a lack of comprehensive discussion on the various material property parameters of EMC materials, it is essential to identify the critical influencing factors and quantify the effects of each parameter on wafer warpage. The material properties include Young’s modulus of the epoxy molding compound before and after the glass transition temperature (Tg) range of 25–35 °C (EL) and 235–260 °C (EH), coefficient of thermal expansion (α1, α2), and the temperature change (∆T) between EL and EH. Results show that, within the range of extreme values of material properties, EL and α1 are the critical factors that affect wafer warpage during the decarrier process in fan-out packaging. α1 has a more significant impact on wafer warpage compared with EL. EH, α2, Tg, and ∆T have little influence on wafer warpage. Additionally, the study identified the optimized material property of the epoxy molding compound that can reduce the maximum wafer warpage in the X and Y directions from initial values of 7.34 mm and 7.189 mm to 0.545 mm and 0.45 mm, respectively, resulting in a reduction of wafer warpage of 92.58% (X direction) and 93.74% (Y direction). Thus, this study proposes an approach for evaluating the impact of material properties of epoxy molding compounds on wafer warpage in fan-out wafer-level packaging. The approach aims to address the issue of excessive wafer warpage due to material variation and to provide criteria for selecting appropriate epoxy molding compounds to enhance process yield in packaging production lines.

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“…The FOWLP fabrication process is made up of three basic flows. [14][15][16] Figure 2 shows a simplified image of the manufacturing process flows: The electrical connections between the die and package are implemented by direct RDL formation on the die pad in a die-first (facedown) process; [17,18] RDL formation is performed after CMP using a die-first (face-up) process; [19,20] and flip chip mounting to RDL is performed using solder bumps on the chip in an RDL-first process. [21,22] In this study, a die-first (face-down) process is selected as the manufacturing process because the corresponding mass production technology has already been established.…”

Section: Issues and Solutions For Fowlpmentioning

confidence: 99%

5-in-1 Fan-Out Wafer-Level Packaging Technology with One AI Chip and Four Memory Chips for Internet of Things Modules

Yamashita

Sekiguchi

2021

Transactions of The Japan Institute of Electronics Packaging

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Electrical, Thermal, and Mechanical Characterization of eWLB, Fully Molded Fan-Out Package, and Fan-Out Chip Last Package

Cited by 24 publications

References 18 publications

A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges

A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges

Exploring the Influence of Material Properties of Epoxy Molding Compound on Wafer Warpage in Fan-Out Wafer-Level Packaging

5-in-1 Fan-Out Wafer-Level Packaging Technology with One AI Chip and Four Memory Chips for Internet of Things Modules

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