Electrical properties of the Ti(SiGe)2/Si0.89Ge0.11/Si(001) contact system

Abstract

The electrical properties of a thin ͑350 Å͒ layer deposited on a molecular beam epitaxial grown Si 0.89 Ge 0.11 /Si(001) heterostructure and subsequently annealed at T a ϭ550-800°C were studied in a wide ͑80-325 K͒ temperature range. Annealing at 800°C produces a single reaction product, the C54 phase of Ti͑SiGe͒ 2 , while lower temperature anneals result in the coexistence of a few intermetallic compounds. It was found that while for annealing temperatures lower than 800°C, the Fermi level is pinned with respect to the conduction band, annealing at 800°C results in Fermi level partial pinning with respect to the valence band. The current flow in this case is controlled mainly by thermionic emission in the presence of interface states. Two kinds of traps were observed by deep level transient spectroscopy in the barrier region after the 800°C annealing. Acceptor-like traps with an activation energy of Ϸ0.46-0.5 eV, a capture cross-section a ϭ1.3ϫ10 Ϫ12 cm 2 , and a density D t Ϸ3ϫ10 13 eV Ϫ1 cm Ϫ2 , which most likely originate from the strain relaxation in the SiGe epilayer, were found to be responsible for the partial Fermi level pinning at the interface. Electron traps with an activation energy of Ϸ0.17 eV and a capture cross-section d ϭ7.7ϫ10 Ϫ16 cm 2 were also identified and attributed to the SiGe epilayer; they are assumed to originate from a well-known vacancy-oxygen center.

Material Characterization of Metal Germanide Gate Electrodes Formed by Fully Germanided Gate Process

“…Moreover, germanosilicide is formed easily in several metal/SiGe systems. [8][9][10] In this regard, not only FUGE but also Ge-incorporated FUSI, i.e., fully germanosilicided (FUSIGE) gate, has the potential to provide a new way of tuning È eff . 11) To develop bulk CMOS devices with FUGE or FUSIGE gates, further material characterization is necessary, in view of the inadequate knowledge of physical properties of germanide.…”