Electrical properties of GaAs//indium tin oxide/Si junctions for III–V-on-Si hybrid multijunction cells

Hara, T.; Ogawa, Takasuke; Liang, Jianbo; Araki, Kiyomichi; Kamioka, Takefumi; Shigekawa, Naoteru

doi:10.7567/jjap.57.08rd05

Cited by 9 publications

(11 citation statements)

References 33 publications

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“…In contrast, the p-GaAs=ITO==ITO=n-Si exhibited Schottky-like characteristics with a high interface resistance. A value of 7.9 × 10 −2 Ω•cm 2 was reported 28) for n-GaAs==ITO=Si without annealing, following the formation of a thicker ITO layer only on the n-Si substrate (compared with the thin 20-nm ITO layer in the present work). However, it was reported that this thicker layer could potentially degrade the performance of a solar cell, because the refractive-index difference between ITO and Si might increase the reflectivity, limiting the incident light reaching the Si subcell.…”

supporting

confidence: 56%

“…However, these structures are difficult to fabricate using conventional methods such as vapor-phase epitaxy and high-temperature fusion bonding, owing to the differences in the thermal expansion coefficients and lattice constants between GaN and GaAs or between GaAs and Si. Roomtemperature wafer bonding [20][21][22][23][24][25][26][27][28] using an Ar ion beams [21][22][23][24][25] is a promising approach, as this technique allows the bonding of materials with different coefficients of thermal expansion and lattice constants.…”

mentioning

confidence: 99%

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Room-temperature bonding of GaAs//Si and GaN//GaAs wafers with low electrical resistance

Ajima

Nakamura

Murakami

et al. 2018

Appl. Phys. Express

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The electrical properties of room-temperature bonded wafers made from materials with different lattice constants, such as p-GaAs and n-Si, p-GaAs and n-Si [both with an indium tin oxide (ITO) surface layer], and n-GaN and p-GaAs, were investigated. The bonded p-GaAs//n-Si sample exhibited an electrical interface resistance of 2.8 × 10−1 Ω·cm2 and showed ohmic-like characteristics. In contrast, the bonded p-GaAs/ITO//ITO/n-Si sample showed Schottky-like characteristics. The bonded n-GaN//p-GaAs wafer sample exhibited ohmic-like characteristics with an interface resistance of 2.7 Ω·cm2. To our knowledge, this is the first reported instance of a bonded GaN//GaAs wafer with a low electrical resistance.

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supporting

confidence: 56%

mentioning

confidence: 99%

Room-temperature bonding of GaAs//Si and GaN//GaAs wafers with low electrical resistance

Ajima

Nakamura

Murakami

et al. 2018

Appl. Phys. Express

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“…Concentration depth profiles of O, Ga, and As atoms obtained using XPS measurements suggest that the oxidation markedly occurs at GaAs//ITO interfaces annealed at temperatures higher than 200 °C, which is consistent with the dependence of resistance in GaAs//ITO/ Si junctions on the temperature. 96) These results suggest that annealing brings about the reaction between GaAs and ITO layers and causes the degradation of the electrical properties of GaAs//ITO interfaces. Low temperature process technologies are essential to make full use of ITO as an intermediate layer in III-V-on-Si MJ cells.…”

Section: Resistance Across Bonding Interfaces In Mj Cellsmentioning

confidence: 93%

Heterojunctions fabricated by surface activated bonding–dependence of their nanostructural and electrical characteristics on thermal process

Shigekawa¹,

Liang²,

Ohno

2022

Jpn. J. Appl. Phys.

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Recent achievements in research of heterojunctions fabricated using surface activated bonding (SAB), one of the practically useful direct wafer bonding technologies, are discussed. The response of bonding interfaces to post-bonding annealing is focused. These junctions reveal high thermal tolerance (1000 ○C in case of junctions made of widegap materials) despite difference in coefficients of thermal expansion between bonded materials. Defect layers with a several-nm thickness formed by the surface activation process at the as-bonded interfaces get faint and their electrical and mechanical properties are improved by annealing. These results show that as bonded interfaces are in a metastable state, and novel functional devices are likely to be realized by applying wafer processing steps to SAB-based junctions. Characteristics of III-V//Si multijunction solar cells, GaN-on-diamond high electron mobility transistors, and metal-foil based low-loss interconnects that are fabricated by processing SAB-based junctions are described, and the future prospects are presented.

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“…Representatively, RPD ITO was applied in the silicon-based multijunction cells and the series resistance was effectively reduced due to its high quality and low process-induced damage. 27 To evaluate the damage degree of different ITO deposition methods, the interface defect density (D it ) at the Si/SiO 2 interfaces was quantitatively analyzed by depositing the same thickness films. The D it in the RPD ITO process is about 1 × 10 10 cm −2 eV −1 , far less than that in the magnetron sputtering method (7.5 × 10 10 cm −2 eV −1 ).…”

Section: Introductionmentioning

confidence: 99%

“…As a soft method, RPD has been applied in the preparation of TCO films in the fabrication of solar cells and was repeatedly reported to play an active role in preventing damage to the as-deposited function layer films. Representatively, RPD ITO was applied in the silicon-based multijunction cells and the series resistance was effectively reduced due to its high quality and low process-induced damage . To evaluate the damage degree of different ITO deposition methods, the interface defect density ( D it ) at the Si/SiO 2 interfaces was quantitatively analyzed by depositing the same thickness films.…”

Section: Introductionmentioning

confidence: 99%

Stable Indium Tin Oxide with High Mobility

Yuan

Liu

et al. 2022

ACS Appl. Mater. Interfaces

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Indium tin oxide (ITO) is widely used in a variety of optoelectronic devices, occupying a huge market share of $1.7 billion. However, traditional preparation methods such as magnetron sputtering limit the further development of ITO in terms of high preparation temperature (>350 °C) and low mobility (∼30 cm 2 V −1 s −1 ). Herein, we develop an adjustable process to obtain high-mobility ITO with both appropriate conductivity and infrared transparency at room temperature by a reactive plasma deposition (RPD) system, which has many significant advantages including low-ion damage, low deposition temperature, large-area deposition, and high throughput. By optimizing the oxygen flow during the RPD process, ITO films with a high mobility of 62.1 cm 2 V −1 s −1 and a high average transparency of 89.7% at 800−2500 nm are achieved. Furthermore, the deposited ITO films present a smooth surface with a small roughness of 0.3 nm. The stability of ITO films to heat, humidity, radiation, and alkali environments is also investigated with carrier mobility average changes of 19.3, 4.4, and 4.7%, showcasing strong environmental adaptability. We believe that stable ITO films with high mobility prepared by a low-damage deposition method will be widely used in full spectral optoelectronic applications, such as tandem solar cells, infrared photodetectors, light-emitting diodes, etc.

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Electrical properties of GaAs//indium tin oxide/Si junctions for III–V-on-Si hybrid multijunction cells

Cited by 9 publications

References 33 publications

Room-temperature bonding of GaAs//Si and GaN//GaAs wafers with low electrical resistance

Room-temperature bonding of GaAs//Si and GaN//GaAs wafers with low electrical resistance

Heterojunctions fabricated by surface activated bonding–dependence of their nanostructural and electrical characteristics on thermal process

Stable Indium Tin Oxide with High Mobility

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