Electrical performance of 130 nm PD-SOI MOSFET with diamond layout

Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment

“…These new effects are: LCE, PAMDLE, DEPAMBBRE [14][15][16][17][18][19] that are able to boost its electrical performance. Some examples of this approach are the Diamond [14][15][16][17][18][19][20][21][22], Octo [23][24][25][26][27], Ellipsoidal [28] and Fish [29] The Octo layout style for MOSFETs was specially invented in order to further boost the Electrostatic Discharge (ESD) tolerance and increase the breakdown voltage (BVDS) as compared to those one found in the Diamond (hexagonal gate shape) layout style. The same effects found (LCE, PAMDLE and DEPAMBBRE) in the Diamond SOI MOSFET also exist in the OSM structure, in which the LCE in the OSM structure is more pronounced, because in this case, it is possible to find a higher resultant longitudinal electric field (LEF).…”

“…The same effects found (LCE, PAMDLE and DEPAMBBRE) in the Diamond SOI MOSFET also exist in the OSM structure, in which the LCE in the OSM structure is more pronounced, because in this case, it is possible to find a higher resultant longitudinal electric field (LEF). This can be justified due to the presence of three longitudinal electric field components instead two of the Diamond SOI MOSFET [21][22][23][24][25][26][27].…”

“…Several references about the Octagonal SOI MOSFET (OSM) describe its better performance in terms of saturation drain current (IDS), transconductance (gm), gm/IDS ratio, voltage gain (AV), unit voltage gain frequency (fT), RON, ILEAK, ION, IOFF and ION/IOFF ratio, as compared to those observed in the rectangular SOI MOSFET (RSM) counterparts, regarding the same gate areas (AG) and bias conditions in room-temperature environments [14][15][16][17][18][19][20][21][22][23][24][25][26][27].…”

Otimização de projetos de circuitos integrados cmos analógicos utilizando-se o imtgspice, otas cascateados e mosfets do tipo diamante

“…al, 2014a). Outra abordagem alternativa, utilizada neste projeto de pesquisa, mas praticamente ainda não utilizada pelas empresas de CI CMOS, é a aplicação de estilos de leiaute de porta não convencionais, como a estrutura inovadora de porta em formato hexagonal para MOSFETs (GIMENEZ, 2016;LIU et. al, 2018).…”

“…Figura 18-Evolução dos transistores em função do tempo. Essa geometria inovadora pode melhorar o desempenho elétrico e a tolerância às variações do processo produtivo e condições ambientais dos MOSFETs (GIMENEZ, 2016;LIU et. al, 2018).…”