Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs

Júnior, José Roberto Banin; Moreto, Rodrigo Alves de Lima; Silva, Gabriel Augusto da; Thomaz, Carlos Eduardo; Gimenez, Salvador Pinillos

doi:10.1007/s10470-020-01750-6

Analog Integr Circ Sig Process

2020

DOI: 10.1007/s10470-020-01750-6

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Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs

José Roberto Banin Júnior

Rodrigo Alves de Lima Moreto

Gabriel Augusto da Silva

et al.

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Cited by 4 publications

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An integrated electrocircuit configuration majorization approach based on boundary constraint and mimetic backouting mechanism

Su,

Quan

2023

2023 3rd International Conference on Electrical Engineering and Control Science (IC2ECS)

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Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs

Cited by 4 publications

References 11 publications

An integrated electrocircuit configuration majorization approach based on boundary constraint and mimetic backouting mechanism

An integrated electrocircuit configuration majorization approach based on boundary constraint and mimetic backouting mechanism

Optimizing a Robust Miller OTA Implemented with Diamond Layout Style for MOSFETs By Using iMTGSPICE

Zero Temperature Coefficient Study Regarding the Half-Diamond Layout Style for MOSFETs

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