Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

Savidis, Ioannis; Alam, Syed Q.; Jain, Ankur; Pozder, Scott; Jones, Robert E.; Chatterjee, Ritwik

doi:10.1016/j.mejo.2009.10.006

Cited by 75 publications

(19 citation statements)

References 11 publications

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“…We performed place---and---route, using Cadence Encounter, to have precise power and area estimations. Depending on the technology and manufacturing process, the pitches of TSVs can range from 1µμm to 10µμm square [37]. In this work, the pad size for TSVs is assumed to be 5µμm 2 with pitch of around 8µμm 2 .…”

Section: Application Traffic Profilementioning

confidence: 99%

Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing

Ebrahimi

Daneshtalab

Liljeberg

et al. 2014

IEEE Trans. Comput.

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Abstract-combining the benefits of 3D ICs and Networks-on-Chip (NoCs) schemes provides a significant performance gain in Chip Multi-Processors (CMPs) architectures. As multicast communication is commonly used in cache coherence protocols for CMPs and in various parallel applications, the performance of these systems can be significantly improved if multicast operations are supported at hardware level. In this paper, we present several partitioning methods for the path-based multicast approach in 3D mesh-based NoCs, each with different levels of efficiency. In addition, we develop novel analytical models for unicast and multicast traffic to explore the efficiency of each approach. In order to distribute the unicast and multicast traffic more efficiently over the network, we propose Minimal and Adaptive Routing (MAR) algorithm for the presented partitioning methods. The analytical and experimental results show that an advantageous method named Recursive Partitioning (RP) outperforms the other approaches. RP recursively partitions the network until all partitions contain a comparable number of switches and thus the multicast traffic is equally distributed among several subsets and the network latency is considerably decreased. The simulation results reveal that the RP method can achieve performance improvement across all workloads while performance can be further improved by utilizing the MAR algorithm. 19% average and 42% maximum latency reduction is obtained on SPLASH-2 and PARSEC benchmarks running on a 64-core CMP.

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Section: Application Traffic Profilementioning

confidence: 99%

Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing

Ebrahimi

Daneshtalab

Liljeberg

et al. 2014

IEEE Trans. Comput.

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“…Depending on the technology and manufacturing process, the pitches of TSVs can range from 1μm to 10μm square [36]. In this work, the pad size for TSVs is assumed to be 5μm square with pitch of around 8µm.…”

Section: Hardware Overheadmentioning

confidence: 99%

Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model

Ebrahimi

Daneshtalab

Liljeberg

et al. 2011

Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

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Three-Dimensional (3D) integration is a solution to the interconnect bottleneck in Two-Dimensional (2D) MultiProcessor System on Chip (MPSoC). 3D IC design improves performance and decreases power consumption by replacing long horizontal interconnects with shorter vertical ones. As the multicast communication is utilized commonly in various parallel applications, the performance can be significantly improved by supporting of multicast operations at the hardware level. In this paper, we propose a set of partitioning approaches each with a different level of efficiency. In addition, we present an advantageous method named Recursive Partitioning (RP) in which the network is recursively partitioned until all partitions contain comparable number of nodes. By this approach, the multicast traffic is distributed among several subsets and the network latency is considerably decreased. We also present Minimal Adaptive Routing (MAR) algorithm for the unicast and multicast traffic in 3D-mesh Networks-on-Chip (NoCs). The idea behind the MAR algorithm is utilizing the Hamiltonian path to provide a set of alternative paths.

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“…Vias are interconnects commonly found on multilayer printed or integrated circuits [13][14]. Often, they provide some path to ground or to other device via some RDL (Re-Distribution Layer).…”

Section: Via Electromagnetic Behaviourmentioning

confidence: 99%

Insights into Three-Dimensional Radiofrequency Circuits Connections

Dahmani¹,

Valorge²,

Sun³

et al. 2011

CTA

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Abstract:The authors state briefly the possibility of various simulators to handle propagation of electromagnetic waves along some interconnections, in 3D RF (Radio Frequency) circuits. The studies are first derived in the time domain: a Finite-Difference Time-Domain method is applied, taking spectra via FFTs (Fast Fourier Transform) as post-processors. Electric and magnetic field distributions, pulse propagations along stripline structures or vias are highlighted. The scattering parameters for various cases are extracted and compared. Some original issue of this work is an insight on crosstalk or shielding phenomena between lines.

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Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

Cited by 75 publications

References 11 publications

Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing

Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing

Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model

Insights into Three-Dimensional Radiofrequency Circuits Connections

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