Electrical characterization of true Silicon-On-Nothing MOSFETs fabricated by Si layer transfer over a pre-etched cavity

Kilchytska, Valeriya; Chung, Tsung Ming; Olbrechts, Benoit; Vovk, Ya. N.; Raskin, Jean‐Pierre; Flandre, Denis

doi:10.1016/j.sse.2007.07.021

Cited by 33 publications

(16 citation statements)

References 16 publications

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“…In this context, different fabrication processes of SON structures have been proposed. 1,3- 8 Recently, it has been demonstrated that various void structures, such as spherical, pipe-shaped, and plate-shaped voids, can be formed in Si substrates through spontaneous reshaping of patterned Si substrates by annealing above 1000°C in hydrogen ambient. [3][4][5] This process enables the fabrication of a good crystalline quality SON layer.…”

Section: Introductionmentioning

confidence: 99%

Void shape evolution and formation of silicon-on-nothing structures during hydrogen annealing of hole arrays on Si(001)

Sudoh

Iwasaki

Hiruta

et al. 2009

Journal of Applied Physics

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We have studied the structural evolution of voids in the Si substrate and the formation of silicon-on-nothing ͑SON͒ structures upon spontaneous reshaping of square arrays of cylindrical holes on Si͑001͒ substrates by hydrogen annealing. Vertically elongated voids covered with ͕111͖, ͕100͖, ͕110͖, and ͕113͖ facets are initially formed by the closure of the hole inlets. This step is followed by volume preserving shape changes of the faceted voids in the bulk Si. In situations where the hole-hole separation is sufficiently small, void coalescence occurs due to the shape changes of individual voids, leading to the formation of a SON structure. Until void coalescence, the shapes of individual voids change without being affected by the adjacent voids. Numerical simulations of the shape change of a completely faceted void via solely surface diffusion have been performed and have reproduced the observed shape change.

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Section: Introductionmentioning

confidence: 99%

Void shape evolution and formation of silicon-on-nothing structures during hydrogen annealing of hole arrays on Si(001)

Sudoh

Iwasaki

Hiruta

et al. 2009

Journal of Applied Physics

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“…[11] used the same technique for fabricating silicon on nothing (SON) MOSFET in which the empty layer is created in between the silicon channel region. The principle of the SON process lies in the transfer of high quality thin silicon film over an array of cavities pre-etched into an oxidized silicon bulk wafer by direct wafer bonding [11].…”

Section: Fabrication Feasibilitymentioning

confidence: 99%

“…1) first to make the cavity for back gate patterning and thereafter 2) empty space in between the channel region is created [10,11].…”

Section: Fabrication Feasibilitymentioning

confidence: 99%

Investigation of Empty Space in Nanoscale Double Gate (ESDG) MOSFET for High Speed Digital Circuit Applications

Kumari¹,

Saxena²,

Gupta³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The impact of Empty Space layer in the channel region of a Double Gate (i.e. ESDG) MOSFET has been studied, by monitoring the DC, RF as well as the digital performance of the device using ATLAS 3D device simulator. The influence of temperature variation on different devices, i.e. Double Gate incorporating Empty Space (ESDG), Empty Space in Silicon (ESS), Double Gate (DG) and Bulk MOSFET has also been studied. The electrical performance of scaled ESDG MOSFET shows high immunity against Short Channel Effects (SCEs) and temperature variations. The present work also includes the linearity performance study in terms of VIP 2 and VIP 3 . The proper bias point to get the higher linearity along with the higher transconductance and device gain has also been discussed.

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“…However, it will also introduce short channel effects in sub-nano meter devices that adversely affect the device performance and long-term reliability [1]. Due to better scalability and excellent threshold voltage, roll-off Silicon On Nothing (SON) [2] and Insulated Shallow Extension (ISE [3] architecture become promising candidates at sub-90 nm channel length. In 2011, we proposed new device architecture, i.e., Insulated Shallow Extension Silicon On Nothing (ISE-SON) [4] (as shown in Figure 1a MOSFET) which combined the advantages of both ISE and SON architecture and showed excellent device performance as compared to other two architectures.…”

Section: Introductionmentioning

confidence: 99%

Circuit level implementation for insulated shallow extension silicon on nothing (ISE-SON) MOSFET: A novel device architecture

Kumari¹,

Saxena²,

Gupta³

et al. 2013

IETE J Res

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In this paper, circuit performance of Insulated Shallow Extension Silicon On Nothing (ISESON) architecture is investigated. A comparative analysis of ISESON, Silicon On Nothing (SON), and Insulated Shallow Extension (ISE) architecture has been carried out to explore the potential of the devices for low-voltage digital applications, i.e., in terms of combinational and static sequential circuits. The relatively enhanced device performance, lower parasitic capacitances, and improved reliability issues in terms of interface charges at the SiO 2 /Si interface of ISE-SON over SON, and ISE MOSFET for 22 nm channel length proves the suitability of the architecture for low-voltage digital applications.

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Electrical characterization of true Silicon-On-Nothing MOSFETs fabricated by Si layer transfer over a pre-etched cavity

Cited by 33 publications

References 16 publications

Void shape evolution and formation of silicon-on-nothing structures during hydrogen annealing of hole arrays on Si(001)

Void shape evolution and formation of silicon-on-nothing structures during hydrogen annealing of hole arrays on Si(001)

Investigation of Empty Space in Nanoscale Double Gate (ESDG) MOSFET for High Speed Digital Circuit Applications

Circuit level implementation for insulated shallow extension silicon on nothing (ISE-SON) MOSFET: A novel device architecture

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