Circuit level implementation for insulated shallow extension silicon on nothing (ISE-SON) MOSFET: A novel device architecture

Abstract

In this paper, circuit performance of Insulated Shallow Extension Silicon On Nothing (ISESON) architecture is investigated. A comparative analysis of ISESON, Silicon On Nothing (SON), and Insulated Shallow Extension (ISE) architecture has been carried out to explore the potential of the devices for low-voltage digital applications, i.e., in terms of combinational and static sequential circuits. The relatively enhanced device performance, lower parasitic capacitances, and improved reliability issues in terms of interface charges at the SiO 2 /Si interface of ISE-SON over SON, and ISE MOSFET for 22 nm channel length proves the suitability of the architecture for low-voltage digital applications.