2013
DOI: 10.4028/www.scientific.net/msf.740-742.911
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Electrical Characterization of PiN Diodes with p<sup>+</sup> Layer Selectively Grown by VLS Transport

Abstract: This paper deals with electrical characterization of PiN diodes fabricated on an 8° off-axis 4H-SiC with a p++localized epitaxial area grown by Vapour-Liquid-Solid (VLS) transport. It provides for the first time evidence that a high quality p-n junction can be achieved by using this technique followed by a High Temperature Annealing (HTA) process.

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Cited by 8 publications
(11 citation statements)
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“…6-a), which is the same on both on-axis and 8°-off epilayers and for both e-beam and sputtering techniques (not shown here). These observations agree with our previous work [9]. SBH and ideality factor vary in the range 1.3 < φ b < 2.8 eV and 1.4 < n < 2.9, respectively.…”
Section: Pin Diode With Peripheral Protectionsupporting
confidence: 94%
See 1 more Smart Citation
“…6-a), which is the same on both on-axis and 8°-off epilayers and for both e-beam and sputtering techniques (not shown here). These observations agree with our previous work [9]. SBH and ideality factor vary in the range 1.3 < φ b < 2.8 eV and 1.4 < n < 2.9, respectively.…”
Section: Pin Diode With Peripheral Protectionsupporting
confidence: 94%
“…In our previous work, it was demonstrated that a rather good PN junction could be achieved by using a 1 µm deep p-type SEG-VLS layer into a n --type 4H-SiC epilayer [9]. As a step forward towards the use of such localized doping process in a functional device, we report here on the fabrication and characterization of PiN diodes using SEG-VLS process for the realization of the p+ doped emitter and guard ring peripheral protection.…”
Section: Pin Diode With Peripheral Protectionmentioning
confidence: 99%
“…The VLS growth has been performed at 1100 C during 5 min with Ar as carrier gas and propane as carbon source. 13 Micro-Raman spectrometry, electron backscatter diffraction phase mapping and transmission electron microscopy observation (not shown here) did not display any evidence of 3 C polytype inclusion. The structure of the TLM pattern is reported in Fig.…”
mentioning
confidence: 99%
“…11,12 Moreover, a high quality p þ (VLS)-n junction can be achieved by using this technique, which offers new prospects for the achievement of new power electronics devices, including deeply buried peripheral protection zones such as guard rings or Junction Barrier Schottky (JBS) structures. 13 This paper presents a study of ohmic contacts properties realized on p þ À type 4 H-SiC buried SEG-VLS layer.…”
mentioning
confidence: 99%
“…In order to compare our results with those previously presented in [6], breakdown voltage tests were performed under the same conditions, i.e. in air and at room temperature.…”
Section: Resultsmentioning
confidence: 93%