Electrical Characterization of FEOL Bridge Defects in Advanced Nanoscale Devices Using TCAD Simulations

Wei, Teo Chea; Narang, Vinod; Thean, Aaron

doi:10.1109/ipfa.2018.8452518

Cited by 3 publications

(6 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Finally, based on the abovementioned device structure and simulation models, the current−voltage characteristics from the simulations are correlated with those from the measurements. 56 Our simulated transfer characteristics versus gate bias (I D /I S −V G ) are in qualitative agreement with the ones of the actual device (Supporting Information Figure S1 and S2), validating our simulation structures and models. Two-Stage Verification Process.…”

Section: ■ Materials and Methodssupporting

confidence: 82%

“…In comparison, the GAA-FET, with its entire channel region fully wrapped by the gate electrode, has superior electrostatic integrity, as shown in Figure b(i). , It is the potential device architecture for the ultimate technology nodes. The common defects found in ICs include open, short, transistor drive strength, transistor leakage, and port bridge/open; in this work, we focus on bridge defects in the FinFET and GAA-FET. , We modeled these bridge defects as a titanium nitride (TiN) resistive metal, as they are commonly created during the gate patterning and chemical–mechanical polishing (CMP) , processes.…”

Section: Results and Discussionmentioning

confidence: 99%

“…The device simulation setup consisting of the drift–diffusion model, the van Dort quantization model, mobility degradation, Shockley–Read–Hall (SRH) recombination, and direct tunneling is implemented. By correlating the bridge defect simulation results and actual measurement results, the surrogate model is validated for bridge defects throughout the device . The simulated drain/source current versus gate voltage characteristics ( I D / I s – V G ) give a qualitative resemblance to the I – V behavior of the actual device.…”

Section: Results and Discussionmentioning

confidence: 99%

“…The common defects found in ICs include open, short, transistor drive strength, transistor leakage, and port bridge/open; in this work, we focus on bridge defects in the FinFET 55 and GAA-FET. 24,56 We modeled these bridge defects as a titanium nitride (TiN) resistive metal, as they are commonly created during the gate patterning and chemical−mechanical polishing (CMP) 57,58 processes.…”

Section: ■ Results and Discussionmentioning

confidence: 99%

“…Actual defects in the physical FinFET devices from the semiconductor industry are used as the golden reference for our TCAD model calibration. Based on the actual physical characteristic of the bridge defect captured by the STEM image shown in Figure 1b(v), a similar 3D single-fin FinFET structure 56 is modeled using Sentaurus Device structure Editor (SDE), 60 as shown in Figure 2a−c. The detailed methodology and setup are described in the Materials and Methods section.…”

Section: ■ Results and Discussionmentioning

confidence: 99%

See 4 more Smart Citations

Transfer Learning-Based Artificial Intelligence-Integrated Physical Modeling to Enable Failure Analysis for 3 Nanometer and Smaller Silicon-Based CMOS Transistors

Pan

Low

Ghosh

et al. 2021

ACS Appl. Nano Mater.

View full text Add to dashboard Cite

Integral to the success of the semiconductor industry in keeping up with Moore's law is the importance of failure analysis (FA). Accurate and fast FA is vital in ensuring yield, reliability, and rapid production in the semiconductor industry. However, locating defects among tens of billions of transistors packed in the tiny modern microchip is not a trivial task. Not only the process technology has to achieve such high integration of devices evolved to become astoundingly sophisticated but also debugging for defects in these chips has become remarkably complex. With electrical nanoprobing, we show how artificial intelligence-integrated physical modeling can be effective in finding difficult proverbial needle-in-a-haystack defects based on the electrical responses of the devices. Moreover, the information learned on current devices can be transferred to the latest transistor technologies, enabling machine learning-based defect sleuths of the future. Notably, we achieved a defect region classification accuracy of 99.5% on well-studied fin nanoscale field-effect transistors (FET) using a defect dataset based on an experimentally calibrated TCAD digital twin model and an adaptive boundary refinement technique. With transfer learning, a defect region classification accuracy of 99.58% is also achieved on the next-generation gate-allaround FETs, overcoming the lack of crucial datasets and optimized labels to guide and accelerate the production process of emerging devices. The proposed technique is expected to be the next level of defect identification, an important stepping stone to accelerate the production process for advanced technology nodes beyond 3 nm.

show abstract

Section: ■ Materials and Methodssupporting

confidence: 82%