Electric Field Induced Nitride Trapped Charge Lateral Migration in a SONOS Flash Memory

Liu, Yuheng; Jiang, Cheng-Min; Chen, Wei‐Chun; Wang, Tahui; Tsai, Wen-Jer; Lu, Tsung-Chien; Chen, Kuang-Chao; Lu, Chih‐Yuan

doi:10.1109/led.2016.2633545

Cited by 27 publications

(5 citation statements)

References 11 publications

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“…Published single-cell data ( Figure 36) suggest that a good intrinsic retention can be achieved, as expected from a floating-gate design [289]. The retention properties of charge-trap based planar devices have been extensively investigated as a function of temperature and bias [300], pointing out the roles of vertical charge loss through the tunnel oxide and lateral charge migration in the nitride [301][302][303][304], which also reduces the stored charge located above the channel region, that determines V T . In 3D devices, the importance of such effects is shown in Figure 37, where lateral diffusion along the nitride is modulated by the state of adjacent cells [305]: having all cells programmed decreases the concentration gradient, slowing down diffusion and reducing the V T shift.…”

Section: Retentionmentioning

confidence: 78%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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Section: Retentionmentioning

confidence: 78%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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“…The ≈20 nm SiO 2 thickness, however, is already quite close to the thickness scaling limit. This is because the trapped electrons in the CTL migrate to the neighboring cells via the thermal emission or hopping mechanism through the trap sites within the SiN x layer . When the isolation distance (SiO 2 thickness) decreases, such a problem becomes more serious .…”

Section: Planar and Vertical Nand Scaling Limitmentioning

confidence: 99%

What Will Come After V‐NAND—Vertical Resistive Switching Memory?

Yoon

Kim

Hwang

2019

Adv Elect Materials

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The NAND flash memory serves as the key enabler of the flourishing of portable handheld information devices, such as the cellular phone. The recent upsurge in the sales of vertical NAND flash memory (V‐NAND) entails a further increase in the available information capacity at the edge devices and the servers with higher performance and lower power consumption compared with the magnetic hard‐disc drives. Nonetheless, there will certainly be an upper limit for the number of stacked layers, which will be the point at which further memory density increase will stop. While V‐NAND is a supreme outcome of semiconductor memory technologies, it still relies on conventional Si‐based materials. The newly explored memory materials and concepts, such as the resistance‐based memories, can therefore be an appealing contender to or successor of V‐NAND. In this review, the current state of V‐NAND is first briefly looked into, and then the eventual limitation of memory density increase and performance boost are discussed. Most importantly, the possible strategies of integrating the resistance‐based memories into the vertical architecture are then discussed. Finally, the outlook for such resistance‐based vertical memories is presented.

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“…The cause of vertical loss is the trapped charges of nitride passing through the tunneling oxide [12][13][14]. Lateral charge spreading is caused by the electric field [15][16] from charges in WL spaces and adjacent cells. Charge loss has a greater impact on 3D NAND flash memory as it is scaled down, and there is a steady stream of research about this [17][18][19][20][21][22].…”

Section: Introductionmentioning

confidence: 99%

Improvement of Retention Characteristics Using Doped SiN Layer Between WL Spaces in 3D NAND Flash

Kyung,

Suh,

Jung

et al. 2024

IEEE Access

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We propose a novel structure of a charge trapping layer, that is doped between Word Line(WL) spaces in 3D NAND flash memory. To estimate the retention characteristics, the ∆Vth of each structure by doping type is compared to a reference structure during retention operation. In this study, lateral charge spreading, rather than vertical loss, is mainly studied as an indicator to determine how long stored data can survive on the selected cell. When the SiN layer is doped with p-type, the electrostatic potential decreases and SRH recombination increases in the doping region. As a result, the p-type doping structure has better retention characteristics than others. In addition, for an optimized structure between retention characteristics and cell current, the doping region of the SiN layer is split and analyzed by the thickness of the doping region. Since the p-type doping region is thicker, lateral spreading is effectively blocked although the cell current decreased slightly.

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Electric Field Induced Nitride Trapped Charge Lateral Migration in a SONOS Flash Memory

Cited by 27 publications

References 11 publications

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

What Will Come After V‐NAND—Vertical Resistive Switching Memory?

Improvement of Retention Characteristics Using Doped SiN Layer Between WL Spaces in 3D NAND Flash

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