Electric circuit model for strained-layer epitaxy

Kujofsa, Tedi; Ayers, J. E.

doi:10.1088/0268-1242/31/11/115014

Cited by 17 publications

(16 citation statements)

References 16 publications

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“…The effective stress is given by = , [2] where is the in-plane strain, is the equilibrium in-plane strain, and is a variable of integration. The equilibrium strain is determined at each step in time using a numerical energy minimization approach (7) or an electrical circuit model for the strained heterostructure (8). The length of misfit dislocations is found by integrating the glide velocity and multiplying by two to account for growth of a misfit dislocation from both sides:…”

Section: Dtka Model For Lattice Relaxationmentioning

confidence: 99%

(Invited) Recent Advances in the Modeling of ZnS_ySe_1-y/ GaAs (001) Heterostructures with Application to Dislocation Sidewall Gettering

Ayers¹,

Kujofsa²,

Raphael

2021

ECS Trans.

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In this paper we describe state-of-the-art approaches to the modeling of strain relaxation and dislocations in ZnSSe/GaAs (001) heterostructures, with applications to dislocation sidewall gettering (DSG) in devices. Current modeling approaches are based on the extension of the original Dodson and Tsao plastic flow model [B. W. Dodson and J. Y. Tsao, Appl. Phys. Lett., 51, 1325 (1987); Appl. Phys. Lett., 52, 852 (1988)] to include compositional grading and multilayers, dislocation interactions, and differential thermal expansion. Important recent breakthroughs have greatly enhanced the utility of these modeling approaches in three respects: i) pinning interactions have been included in graded and multilayered structures, providing a better description of the rate of strain relaxation as well as the limiting value; ii) a refined model describing the interaction length for dislocation-dislocation interactions was formulated to include jogging in compositionally-graded and step-graded layers; and iii) inclusion of back-and-forth weaving of dislocations provides a more accurate description of heterostructures containing strain reversals, such as strained-layer superlattices or overshoot graded layers. We will describe these three key advances and use reasonable estimates of the kinetic parameters for ZnSSe to explain and illustrate practical features of dislocation sidewall gettering in II-VI heterostructures.

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Section: Dtka Model For Lattice Relaxationmentioning

confidence: 99%

(Invited) Recent Advances in the Modeling of ZnS_ySe_1-y/ GaAs (001) Heterostructures with Application to Dislocation Sidewall Gettering

Ayers¹,

Kujofsa²,

Raphael

2021

ECS Trans.

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“…Here the equilibrium in-plane strain is determined at each step in time using a numerical energy minimization approach 14 or an electrical circuit model for the strained heterostructure. 15 The length of misfit dislocations L MD z ð Þ at a distance z from the interface is given by…”

Section: Plastic Flow Model Including Pinningmentioning

confidence: 99%

Dislocation Sidewall Gettering in II-VI Semiconductors and the Effect of Dislocation Pinning Interactions

Kujofsa

Ayers

2020

Journal of Elec Materi

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It has been shown that threading dislocations may be removed from patterned mismatched heteroepitaxial layers through a process of dislocation sidewall gettering (DSG), also known as patterned heteroepitaxial processing (PHeP). This gettering approach involves the glide of dislocations toward sidewalls, where they become trapped by image forces. Simple quantitative models have been developed for DSG, but they fail to explain why only partial removal of dislocations was observed in ZnSSe/GaAs (001) whereas complete removal has been achieved in ZnSe/GaAs (001) with higher lattice mismatch. Until now this phenomenon has been qualitatively explained by the presence of sessile dislocations. Here we present a quantitative model for pinning interactions and show that these interactions can limit the growth of misfit dislocation segments and thereby reduce the effectiveness of DSG in ZnS y Se 1-y /GaAs (001) relative to ZnSe/GaAs (001).

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“…] and 0 0  f corresponds to the substrate. Further details of the ECM have been published previously 19 .…”

Section: Theorymentioning

confidence: 99%

Chirped Superlattices as Adjustable Strain Platforms for Metamorphic Semiconductor Devices

et al. 2017

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Chirped superlattices are of interest as buffer layers in metamorphic semiconductor device structures, because they can combine the mismatch accommodating properties of compositionally-graded layers with the dislocation filtering properties of superlattices. Important practical aspects of the chirped superlattice as a buffer layer are the surface strain and surface in-plane lattice constant. In this work we studied two basic types of InGaAs/GaAs chirped superlattice buffers; type I is compositionally modulated while type II is thicknesses modulated. For both types, we have investigated the equilibrium surface strain and surface in-plane lattice constant, and have compared the behavior to linearly-graded buffers having the same top target composition of indium.

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Electric circuit model for strained-layer epitaxy

Cited by 17 publications

References 16 publications

(Invited) Recent Advances in the Modeling of ZnS_ySe_1-y/ GaAs (001) Heterostructures with Application to Dislocation Sidewall Gettering

(Invited) Recent Advances in the Modeling of ZnS_ySe_1-y/ GaAs (001) Heterostructures with Application to Dislocation Sidewall Gettering

Dislocation Sidewall Gettering in II-VI Semiconductors and the Effect of Dislocation Pinning Interactions

Chirped Superlattices as Adjustable Strain Platforms for Metamorphic Semiconductor Devices

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Electric circuit model for strained-layer epitaxy

Cited by 17 publications

References 16 publications

(Invited) Recent Advances in the Modeling of ZnSySe1-y / GaAs (001) Heterostructures with Application to Dislocation Sidewall Gettering

(Invited) Recent Advances in the Modeling of ZnSySe1-y / GaAs (001) Heterostructures with Application to Dislocation Sidewall Gettering

Dislocation Sidewall Gettering in II-VI Semiconductors and the Effect of Dislocation Pinning Interactions

Chirped Superlattices as Adjustable Strain Platforms for Metamorphic Semiconductor Devices

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(Invited) Recent Advances in the Modeling of ZnS_ySe_1-y/ GaAs (001) Heterostructures with Application to Dislocation Sidewall Gettering

(Invited) Recent Advances in the Modeling of ZnS_ySe_1-y/ GaAs (001) Heterostructures with Application to Dislocation Sidewall Gettering