Several simple models have been developed for the threading dislocation behavior in heteroepitaxial semiconductor materials. Tachikawa and Yamaguchi [Appl. Phys. Lett., 56, 484 (1990)] and Romanov et al. [Appl. Phys. Lett., 69, 3342 (1996)] described models for the annihilation and coalescence of threading dislocations in uniform-composition layers, and Kujofsa et al. [J. Electron. Mater., 41, 2993 (2013)] extended the annihilation and coalescence model to compositionally-graded and multilayered structures by including the misfit dislocation-threading dislocation interactions. However, an important limitation of these previous models is that they involve empirical parameters. The goal of this work is to develop a predictive model for annihilation and coalescence of threading dislocations which is based on the dislocation interaction length Lint. In the first case if only in-plane glide is considered the interaction length is equal to the length of misfit dislocation segments while in the second case glide and climb are considered and the interaction length is a function of the distance from the interface, the length of misfit dislocations, and the density of the misfit dislocations. In either case the interaction length may be calculated using a model for dislocation flow. Knowledge of the dislocation interaction length allows predictive calculations of the threading dislocation densities in metamorphic device structures and is of great practical importance. Here we demonstrate the latter model based on glide and climb. Future work should compare the two models to determine which is more relevant to typical device heterostructures.
Metamorphic semiconductor devices such as high electron mobility transistors (HEMTs), light-emitting diodes (LEDs), laser diodes, and solar cells are grown on mismatched substrates and typically exhibit a high degree of lattice relaxation. In order to minimize the incorporation of threading defects it is common to use a linearly-graded buffer layer to accommodate the mismatch between the substrate and device layers. However, some work has suggested that buffer layers with non-linear grading could offer superior performance in terms of limiting the surface density of threading defects. In this work, we have compared S-graded buffer layers with different orders and thicknesses. To do so we calculated the expected surface threading dislocation density for each buffer design assuming a GaAs (001) substrate. The threading dislocation densities were calculated using the LMD model, in which the coefficient for second-order annihilation and coalescence reactions between threading dislocations is considered to be equal to the length of misfit dislocations.
We conducted a modeling study of the threading dislocation behavior in chirped and unchirped InGaAs/GaAs (001) strained-layer superlattices (SLSs) using a Dodson & Tsao / Kujofsa & Ayers (DTKA) type plastic flow model. Four types of SLSs were investigated: type I was chirped using compositional modulation, type II was chirped using layer thickness modulation, type III was unchirped with alternating layers of InGaAs and GaAs, and type IV was unchirped with alternating layers of InGaAs having two different compositions. Generally the surface and average values of the dislocation density decreased with increasing total thickness. The dependence on top indium composition was more complex, due to dislocation compensation and multiplication effects, but for type II and IV superlattices, the average and surface threading dislocation densities increased in nearly monotonic fashion with top indium composition. Based on these results, the compositionally-modulated chirped (type I) and InGaAs/GaAs unchirped (type III) superlattices appear to be best suited as buffer layers for metamorphic devices, while the chirped superlattices with layer thickness modulation (type II) and InGaAs/InGaAs unchirped (type IV) superlattices appear to be poorly suited for use as buffer layers for devices containing high indium content.
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