Efficient Totally Self-Checking Shifter Design

Abstract

International audienceSelf-checking designs will gain increasing interest in industrial applications if they satisfy the following requirements: high fault coverage, reduced hardware cost and reduced design effort. This work is aimed to reach these requirements for the design of self-checking shifters and is part of a broader project concerning the design of self-checking data paths

Carry checking/parity prediction adders and ALUs

“…Thus, these blocks can be checked by the parity code. In addition, although some interactions exist between the bit slices of a shifter, single-position and multiple-position shifters can also achieve the fault secure property by means of the parity code (see, e.g., [17]). Obviously, adding a parity bit to the buses and the register file involves low hardware overhead (e.g., 6.25% for a 16-bits data length).…”

“…Hardware overhead is also low for the self-checking shifter. For instance, the hardware overhead for a 16-bits shifter performing rotation, arithmetic shift, and left and right logic shifts for any number of positions, is only 18% ( [17]). Tables I and II. It is interesting to compare this cost with the cost of other self-checking adder and ALU designs.…”