Efficient tests for realistic faults in dual-port SRAMs

Hamdioui, Said; Goor, A.J. van de

doi:10.1109/tc.2002.1004586

Cited by 32 publications

(18 citation statements)

References 15 publications

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“…However, to test for bridging faults in the write and read data busses of the RAM, March LR with BDS is used to test the 256 16-bit mode. Since the block RAMs are true dual-port RAMs, two additional march algorithms (March d2pf and March s2pf [7]) are used to implement the TPG to test dual-port access of the RAMs. A total of seven RAM BIST configurations (5 single-port and 2 dual-port) are required to completely test block RAMs.…”

Section: Ram Bist Implementationmentioning

confidence: 99%

A system for automated built-in self-test of embedded memory cores in system-on-chip

Garimella

Stroud

2005

Proceedings of the Thirty-Seventh Southeastern Symposium on System Theory, 2005. SSST '05.

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Abstract-A system for automatic generation of BuiltIn Self-Test (BIST) for embedded memory cores in a system-on-chip (SoC) is presented. The BIST approach tests RAMs of any address and data bus widths and can test both single-port and dual-port RAMs operating in synchronous or asynchronous mode. A Field Programmable Gate Array (FPGA) independent BIST model is developed using VHDL. The parameterized VHDL model has been synthesized and used to test various sizes and types of embedded RAMs in SoCs and FPGAs.

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Section: Ram Bist Implementationmentioning

confidence: 99%

A system for automated built-in self-test of embedded memory cores in system-on-chip

Garimella

Stroud

2005

Proceedings of the Thirty-Seventh Southeastern Symposium on System Theory, 2005. SSST '05.

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“…They are quite straightforward since the spare rows and/or columns can be implemented adjacent to the main memory blocks to share bit-lines (BLs) and/or word-lines (WLs) respectively in a compact layout style. However, full spare rows and columns are obviously no longer efficient for repairing clustered faulty cells and scattered faulty cells due to address faults [8]. Therefore, some infrastructures for remapping are proposed to split into shorter segments [9,10] and/or spare blocks [11].…”

Section: Introductionmentioning

confidence: 99%

High-yield performance-efficient redundancy analysis for 2D memory

Huang

2011

Sci. China Inf. Sci.

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High-yield performance-efficient remapping architecture, repairing algorithms and redundancy analysis (HYPERA) are proposed for 2D memory. The proposed hypercube-based memory repair architecture consists of spare row-like subcubes with a modified ternary CAM with an address concentrator and a parallel sorter-like address concentrator. Generally, for an acceptable repair rate about 3% of spare subcubes and no more than 5% of hardware overhead are required. A modified Quine-McCluskey algorithm and the Essential Cube Pivoting algorithm are also developed for redundancy analysis. Almost 100% of repair rate can be obtained using only 32 equivalent rows under reasonable situations. Under less spare memory the repair rates of proposed approaches can be much higher than most results of previous work. CitationHuang T C. High-yield performance-efficient redundancy analysis for 2D memory.

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“…Smaller size and higher frequency applications introduce new and more complicated SRAM faults, such as transition fault, data retention fault, coupling fault, pattern sensitive fault and so on. To detect these faults, we need not only consider new arithmetics like March Cþ, March LR, March S2PF, March D2PF (van de Goor, Gaydadjiev, Yarmolik, and Mikitjuk 1996;Hamdioui and van de Goor 2002), but also at speed test (Hirabayashi et al 2002;Iyengar et al 2006). And furthermore, we need new method that allows SRAM to be tested at full speed for these faults (Cheng, John Hill and Kebichi 2010).…”

Section: Introductionmentioning

confidence: 99%

An effective BIST scheme for SRAM full speed test

Zhang

Yu²,

Zheng³

et al. 2011

International Journal of Electronics

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This article presents a novel built-in self-test (BIST) scheme at full speed test where access time test is performed. Based on normal BIST circuits, we harness an all digital phase locked loop to generate a high-frequency clock for static random access memory (SRAM) performance test at full speed. A delay chain is incorporated to achieve the four-phase clock. As inputs to SRAM, clock, address, data are generated in terms of the four-phase clock. Key performance parameters, such as access time, address setup and hold times, are measured. The test chip has been fabricated by United Microelectronics Corporation 55 nm CMOS logic standard process. According to test results, the maximum test frequency is about 1.3 GHz, and the test precision is about 35 ps at the typical process corner with supply voltage 1.0 V and temperature 25 C.

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Efficient tests for realistic faults in dual-port SRAMs

Cited by 32 publications

References 15 publications

A system for automated built-in self-test of embedded memory cores in system-on-chip

A system for automated built-in self-test of embedded memory cores in system-on-chip

High-yield performance-efficient redundancy analysis for 2D memory

An effective BIST scheme for SRAM full speed test

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