Efficient Test Solutions for Core-Based Designs

Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits

“…The common idea behind PCTS is to impose a chip-wide maximum allowable limit on power consumption, which should not be exceeded during test application. Several recently proposed powerconstrained test scheduling algorithms aim to maximise the number of tests running in parallel without exceeding this limit [2,9,11,7,6,1,15,12,13].…”

“…INPUT: S, the core set for the target system TCG: the test compatibility graph Tmax = maximum tolerable temperature OUTPUT: Thermal-safe schedule as a list of thermal-safe test sessions Table 1 compares the results obtained using the proposed algorithm with those obtained using the power constrained test scheduling approach presented in [7]. We have chosen the approach presented in [7] for comparison since it is very recent, has been applied to large designs and performs well in comparison with other existing power constrained test scheduling approaches.…”

“…We have chosen the approach presented in [7] for comparison since it is very recent, has been applied to large designs and performs well in comparison with other existing power constrained test scheduling approaches. Details such as floorplan information and realistic test power and time values had to be added or modified in the original design descriptions in order to provide all necessary information for the proposed thermal safe test scheduling algorithms.…”

“…Techniques falling in the first category include low-power scan chain architectures with gated clocks [18,17], scan cell and test pattern reordering [3,5], and low-transition test patterns generated by specialised ATPG algorithms [22] and low-transition TPGs [21]. The second category of techniques is mainly based on powerconstrained test scheduling algorithms [2,9,11,7,6,1,15,12,13] 1 . This paper focuses on avoiding overheating during test through appropriate test scheduling.…”

Design and Optimization of Transparency-Based TAM for SoC Test

“…A number of approaches have been proposed for wrapper and TAM design including test scheduling problem [3]- [10]. These approaches use the infrastructure dedicated to test such as TestBus [11], [12] and TESTRAIL [5] as TAMs, and most of them use the SoC test time as minimization criterion.…”