Design and Optimization of Transparency-Based TAM for SoC Test

Abstract

SUMMARYWe present a graph model and an ILP model for TAM design for transparency-based SoC testing. The proposed method is an extension of a previous work proposed by Chakrabarty with respect to the following three points: (1) constraint relaxation by considering test data flow for each core separately, (2) optimization of the cost for transparency as well as the cost for additional interconnect area simultaneously and (3) consideration of additional bypass paths. Therefore, the proposed ILP model can represent various problems including the same problem as the previous work and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to the previous work.

Wrapper and TAM co-optimization for reuse of SoC functional interconnects

“…They are roughly classified into three types: 1) the method reusing functional buses [6,7], 2) the methods reusing functional networks [8,9] and 3) the methods based on transparency [10,11,12,13]. The wrapper and TAM co-optimization problem to minimize test time was discussed in the methods reusing functional buses and networks while there is no discussion on it in the methods based on transparency.…”