Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)
DOI: 10.1109/vtest.1999.766668
|View full text |Cite
|
Sign up to set email alerts
|

Efficient test generation for transient testing of analog circuits using partial numerical simulation

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1

Citation Types

0
3
0

Publication Types

Select...
4
3

Relationship

0
7

Authors

Journals

citations
Cited by 11 publications
(3 citation statements)
references
References 20 publications
0
3
0
Order By: Relevance
“…Time domain analysis is performed. Piece-wise linear (PWL) transient signal [11,12] is applied to the CUT with use of an arbitrary waveform generator. Exemplary PWL signal is shown in Fig.…”
Section: Proposed Approachmentioning
confidence: 99%
See 1 more Smart Citation
“…Time domain analysis is performed. Piece-wise linear (PWL) transient signal [11,12] is applied to the CUT with use of an arbitrary waveform generator. Exemplary PWL signal is shown in Fig.…”
Section: Proposed Approachmentioning
confidence: 99%
“…Faults classification methods of complex analog circuits are usually based on Simulation Before Test (SBT) methodology [1][2][3][4][5][6][7][8][9][10][11][12][13]. The more probable faults of the CUT are simulated with a pre-defined input stimulus applied to the circuit input.…”
Section: Introductionmentioning
confidence: 99%
“…In transient testing (Gomes and Chatterjee, 1999;Variyam et al, 1999;Burdiek, 2001), the circuit under test (CUT) is excited with a transient test stimulus and the circuit response is sampled at specified time points for fault detection. In this paper a new test signal generation method based on control theory techniques like Pontryagin's maximum principle is presented.…”
Section: Introductionmentioning
confidence: 99%