Efficient systolic architecture for the one-dimensional wavelet transform

Lang, Robert J.; Plesner, Erik; Schröder, Heiko; Spray, A.

doi:10.1117/12.170093

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Cited by 15 publications

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“…In [8] every PE has a local memory of size -l+logN. A systolic control flow generates the proper addressing sequence at each PE and makes data extracted from the local memory also travel to the correct nearby memory element (at distance 2).…”

Section: Systolic 1-dmentioning

confidence: 99%

Wavelet transform architectures: A system level review

Ferretti

Rizzo

1997

Image Analysis and Processing

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Abstract. In this paper we review the architectures designed for wavelet transi:brms, with the purpose to highlight their suitability for inclusion in codec systems. Indeed, common VLSI cost functions (such as AT ~-) are insufficient to evaluate architectures for compression. At the system level, quantization and coding have processing requirements that must be taken into account when designing the transform engine. The hierarchical structure of wavelet transform allows to use "pyramid" algorithms that optimize latency and processor utilization; on-line solutions try to minimize buffering memory. Such approaches can be substituted with more standard ones, if data reordering is mandatory to apply a good quantization strategy. An upcoming commercial solution offers a sound comparison paradigm.

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Section: Systolic 1-dmentioning

confidence: 99%