Efficient Symbolic Simulation via Dynamic Scheduling, Don’t Caring, and Case Splitting

Paruthi, Viresh; Jacobi, Christian; Weber, Kai F.

doi:10.1007/11560548_11

Cited by 3 publications

(3 citation statements)

References 21 publications

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“…The SIMPLIFY operator can be implemented through the constrain, restrict and compact operators with BDDs (as recently analyzed in [10]), or redundancy removal in circuit based representations.…”

Section: A Constrained Transition Relationmentioning

confidence: 99%

“…To the best of our knowledge, the number of scientific works specifically addressing this issue is very limited, although it is important to leverage constraints in order to enhance the overall verification process. For instance, Paruthi et al [10] discuss ways to adopt constraints as don't cares when building BDDs for symbolic simulation. Mony et at.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Speeding up model checking by exploiting explicit and hidden verification constraints

Cabodi¹,

Camurati²,

Garcia³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Constraints represent a key component of stateof-the-art verification tools based on compositional approaches and assume-guarantee reasoning. In recent years, most of the research efforts on verification constraints have focused on defining formats and techniques to encode, or to synthesize, constraints starting from the specification of the design.In this paper, we analyze the impact of constraints on the performance of model checking tools, and we discuss how to effectively exploit them. We also introduce an approach to explicitly derive verification constraints hidden in the design and/or in the property under verification. Such constraints may simply come from true design constraints, embedded within the properties, or may be generated in the general effort to reduce or partition the state space. Experimental results show that, in both cases, we can reap benefits for the overall verification process in several hard-to-solve designs, where we obtain speed-ups of more than one order of magnitude. I. INTRODUCTIONConstraints represent a key component of state-of-the-art simulation and verification tools focusing on compositional verification. In conventional simulation-based frameworks, constraints are very popular to model the environment behavior, often called test-bench. The environment model ensures that only acceptable sequences of values are applied to the design under test. Moreover, the same model can be used to monitor the outputs of the design [1], [2]. In model checking, constraints are used to represent the environment of a block under verification, i.e., the assumptions that the environment must satisfy. Furthermore, constraints are verified as assertions when the design is connected to its real environment. This methodology, usually known as assume-guarantee [3], has gained widespread industrial acceptance [4]. Today, most industrial verification languages, such as PSL [5], CBV [6] and e [7], include constructs to specify constraints.As hundreds of constraints can be necessary to model the environment of commercial designs, in recent years most of the research efforts have focused on two main paths. Along the first one, researchers concentrated on how to encode and represent design constraints [6], [7]. On the second one, research groups have focused on efficient algorithms to synthesize constraints, i.e., to derive them automatically from specifications [8], [9].In this work, our main target is to show how to effectively exploit constraints to improve the performance of model checking algorithms. To the best of our knowledge, the number of scientific works specifically addressing this issue is very

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Section: A Constrained Transition Relationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Speeding up model checking by exploiting explicit and hidden verification constraints

Cabodi¹,

Camurati²,

Garcia³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

show abstract

“…Nevertheless, the data structure is still widely used in industry to solve real-world hardware verification problems, for example at companies such as Intel [23], IBM [24], [29], and Centaur [28]. Furthermore, contemporary commercial FV tools also include BDDs in their spectrum of technologies.…”

Section: Introductionmentioning

confidence: 99%

Universal boolean functional vectors

Bingham

2015

2015 Formal Methods in Computer-Aided Design (FMCAD)

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Abstract-In the simplest setting, one represents a boolean function using expressions over variables, where each variable corresponds to a function input. So-called parametric representations, used to represent a function in some restricted subspace of its domain, break this correspondence by allowing inputs to be associated with functions. This can lead to more succinct representations, for example when using binary decision diagrams (BDDs). Here we introduce Universal Boolean Functional Vectors (UBFVs), which also break the correspondence, but done so such that all input vectors are accounted for. Intelligent choice of a UBFV can have a dramatic impact on BDD size; for instance we show how the hidden weighted bit function can be efficiently represented using UBFVs, whereas without UBFVs BDDs are known to be exponential for any variable order. We show several industrial examples where the UBFV approach has a huge impact on proof performance, the "killer app" being floating point addition, wherein the wide case-split used in the state-of-the-art approach is entirely done away with, resulting in 70-fold reduction in proof runtime. We give other theoretical and experimental results, and also provide two approaches to verifying the crucial "universality" aspect of a proposed UBFV. Finally, we suggest several interesting avenues of future research stemming from this program.

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