Efficient SR-Latch PUF

Habib, Bilal; Kaps, Jens-Peter; Gaj, Kris

doi:10.1007/978-3-319-16214-0_17

Cited by 17 publications

(3 citation statements)

References 19 publications

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“…This configures the flip-flops in a cross-coupled pattern for signature generation. In [33] and [34], latches are utilized for the generation of PUF keys. In this approach, the unknown random state of the latch on start-up is utilized as the source of entropy.…”

Section: A Physical Unclonable Functionsmentioning

confidence: 99%

Resource-efficient PUF Implementation Through FPGA Resource Re-utilization

Vega¹

2023

Preprint

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<p>The Field Programmable Gate Array (FPGA) market has seen significant growth due to the low cost and reduced time to market when compared to ASIC circuits. However, FPGAs' reconfigurable nature introduces security vulnerabilities that can be exploited by adversaries to obtain sensitive information. Physical Unclonable Functions (PUFs) have shown to be valuable security primitives. By leveraging manufacturing variations in a device one can generate unique signatures that can be used for authentication and generation of secret keys. However, PUF implementation can be costly, taking up FPGA resources and requiring long design times. In this paper, we propose a method which takes advantage of the FPGA Look Up Table (LUT) architecture to embed the PUF into functional logic circuits, reducing the cost and design time. We provide detailed implementation guidelines and evaluate the PUF's signature quality and stability under different environmental variations using a set of testbench circuits. Our results demonstrate the effectiveness of our method in securing FPGA designs while reducing implementation costs and design time. </p>

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Section: A Physical Unclonable Functionsmentioning

confidence: 99%

Resource-efficient PUF Implementation Through FPGA Resource Re-utilization

Vega¹

2023

Preprint

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“…Many PUF principles have been published up to now. The most known are memory based PUFs including for example SRAM PUFs [8] and delay based PUFs such as arbiter PUFs [9], ring oscillator PUFs [10], RS latch PUFs [11] and transient effect ring oscillator PUFs [1]. Although some FPGAs, including Flash FPGAs (i.e.…”

Section: Physical Unclonable Functionsmentioning

confidence: 99%

Efficient design of Oscillator based Physical Unclonable Functions on Flash FPGAs

Mureddu

Petura

Bochard

et al. 2017

2017 IEEE 2nd International Verification and Security Workshop (IVSW)

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International audience—With the scaling down of electronic devices and the boom of wireless communications, more and more smart devices are interconnected in what we call the Internet of Things. Connecting devices of everyday use can greatly improve our comfort, but it can also introduce unprecedented security problems. With billions of devices connected there is a huge risk of unauthorized use. In this context, Physical Unclonable Functions (PUFs) are a promising solution since they extract device intrinsic fingerprint that can be used for hardware identification and authentication. Here we present the first fully functional implementation of Oscillator based PUFs on Flash based FPGA. The implementation is presented for the Ring Oscillator based PUF and the Transient Effect Ring Oscillatory based PUF. After explaining those two PUF principles, we give all the necessary design practices to follow to obtain an efficient PUF implementation on Flash FPGA. Finally, we present the characterization of the PUFs and compare it to previous work. To the best of our knowledge, it is the first work which deals with the implementation of Oscillator based PUF on Flash FPGAs. Moreover, all design files are available online to ensure repeatability

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“…One of these groups includes memory based PUF such as the SRAM PUF [11] and the DRAM-PUF [12], [13]. Another group includes delay based PUF such as arbiter PUF [14], ring oscillator (RO) PUF [15], loop PUF [16] and RS latch PUF [17]. Many studies have shown that the RO-PUF is the best candidate for FPGAs (eg.…”

Section: Introductionmentioning

confidence: 99%

Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF

Marchand

Bossuet

Mureddu

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Today, life is becoming increasingly connected. From TVs to smartphones, including vehicles, buildings, and household appliances, everything is interconnected in what we call the "Internet of Things" (IoT). IoT is now part of our life and we have to deal with it. More than 10 billion devices are already connected and five times more are expected to be deployed in the next five years. While deployment and integration of IoT is expanding, one of the main challenge is to provide practical solutions to security, privacy and trust issues in IoT. Protection and security mechanisms need to include features such as interoperability and scalability but also traceability, authentication and access control while remaining lightweight. Among the most promising approaches to such security mechanisms, physical unclonable functions (PUF) provide a unique identifier for similar but different integrated circuits using some of their physical characteristics. These types of functions can thus be used to authenticate integrated circuits, provide traceability and access control. This paper presents a comprehensive case study of the transient effect ring oscillator (TERO) PUF from its implementation on FPGAs to its complete characterization. The implementation of the PUF is detailed for two different families of FPGAs: Xilinx Spartan 6 and Altera Cyclone V. All the metrics used for the characterization are explained in detail and the results of the characterization include robustness to environmental parameters including variations in temperature and voltage. Finally, we compare our results with those obtained for another PUF: the ring oscillator (RO) PUF. All the design files are available online to ensure repeatability and enable comparison of our contribution with other studies.

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Efficient SR-Latch PUF

Cited by 17 publications

References 19 publications

Resource-efficient PUF Implementation Through FPGA Resource Re-utilization

Resource-efficient PUF Implementation Through FPGA Resource Re-utilization

Efficient design of Oscillator based Physical Unclonable Functions on Flash FPGAs

Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF

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