Efficient Software Development Platforms for Multimedia Applications at Different Abstraction Levels

Popovici, Katalin; Guerin, Xavier; Rousseau, Frédéric; Paolucci, P.; Jerraya, Ahmed

doi:10.1109/rsp.2007.21

Cited by 8 publications

(4 citation statements)

References 5 publications

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“…The abstract architecture model hides details of the underlying implementation of the hardware platform, but ensures a sufficient level of control that the software code can be validated in terms of performance, efficiency, and reliable functionality [Popovici et al 2007b]. Both initial application and abstract architecture are inputs of the system.…”

Section: Software Design Stepsmentioning

confidence: 99%

Platform-based software design flow for heterogeneous MPSoC

Popovici

Guerin

Rousseau

et al. 2008

ACM Trans. Embed. Comput. Syst.

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Current multimedia applications demand complex heterogeneous multiprocessor architectures with specific communication infrastructure in order to achieve the required performances. Programming these architectures usually results in writing separate low-level code for the different processors (DSP, microcontroller), implying late global validation of the overall application with the hardware platform. We propose a platform-based software design flow able to efficiently use the resources of the architecture and allowing easy experimentation of several mappings of the application onto the platform resources. We use a high-level environment to capture both application and architecture initial representations. An executable software stack is generated automatically for each processor from the initial model. The software generation and validation is performed gradually corresponding to different software abstraction levels. Specific software development platforms (abstract models of the architecture) are generated and used to allow debugging of the different software components with explicit hardware-software interaction. We applied this approach on a multimedia platform, involving a high performance DSP and a RISC processor, to explore communication architecture and generate an efficient executable code for a multimedia application. Based on automatic tools, the proposed flow increases productivity and preserves design quality. ; Pier Stanislao Paolucci, ATMEL Roma Advanced DSP,

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Section: Software Design Stepsmentioning

confidence: 99%

Platform-based software design flow for heterogeneous MPSoC

Popovici

Guerin

Rousseau

et al. 2008

ACM Trans. Embed. Comput. Syst.

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“…To uncover the design space of complex embedded systems, The Disydent environment should allow for the system performance evaluation at high abstraction levels [9], [23]. Performing simulation at multiple abstraction levels makes it possible to control the speed, required modelling effort, and attainable accuracy of the simulations.…”

Section: E Limitations Of the Disydent Design Flowmentioning

confidence: 99%

“…Performing simulation at multiple abstraction levels makes it possible to control the speed, required modelling effort, and attainable accuracy of the simulations [8]. This enables using a stepwise refinement approach in which abstract simulation models efficiently explore the large design space in the early design stages [9].…”

Section: Introductionmentioning

confidence: 99%

DISYDENT evaluation for the design of multimedia systems

Ammari¹,

Harbegue²,

Jemai

et al. 2008

2008 3rd International Design and Test Workshop

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In this paper, the DIgital SYstem-on-a-chip (SoC) platform-based Design ENvironmenT for shared memory multiple instructions multiple data (MIMD) architectures (DISYDENT) is used. The applicability of the Disydent design flow to systems in the multimedia domain is illustrated. Two case studies typical of multimedia domains will be considered in which the Disydent design-space exploration method is used. The first consists in deploying a medium complexity motion JPEG decoder application onto the ASIM0 multiprocessor MIPS R3000 target platform. In this first study, both modelling and mapping stages of the Disydent design flow are explored for an optimal implementation verifying constraints. The second case study implements a very complex H.264/AVC reference encoder using the same flow. This will demonstrate the limits of the Disydent design flow for the very complex systems and shows the need for a higher level of abstraction than cycle accurate simulations.I.

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“…In this paper, we make use of a Simulink-SystemC MPSoC design flow that focuses on mixed hardware and software refinement from a high-level Simulink model [10]. This Simulink based MPSoC design flow allows concurrent hardware/software design and verification at four abstraction levels: Simulink CAAM, Virtual Architecture, Transaction-accurate model, and Virtual Prototype.…”

Section: Introductionmentioning

confidence: 99%

Simulink-based MPSoC design flow

Huang

Han

Popovici³

et al. 2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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System-level design methodologies have been introduced as a solution to handle the design complexity of embedded multiprocessor SoC (MPSoC) systems. In this paper we describe a system-level design flow starting from Simulink specification, focusing on concurrent hardware and software design and verification at four different abstraction levels: Simulink Combined Algorithm and Architecture Model (CAAM), Virtual Architecture, Transaction-accurate Model and Virtual Prototype. We used two multimedia applications, Motion-JPEG and H.264, to evaluate this design flow. Experimental results show that our design flow can generate various MPSoC architectures from Simulink CAAM correctly and efficiently, allowing processor and task design space exploration at different abstraction levels.

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Efficient Software Development Platforms for Multimedia Applications at Different Abstraction Levels

Cited by 8 publications

References 5 publications

Platform-based software design flow for heterogeneous MPSoC

Platform-based software design flow for heterogeneous MPSoC

DISYDENT evaluation for the design of multimedia systems

Simulink-based MPSoC design flow

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