Efficient simulation of large-scale Spiking Neural Networks using CUDA graphics processors

Nageswaran, Jayram Moorkanikara; Dutt, Nikil; Krichmar, Jeffrey L.; Nicolau, Alex; Veidenbaum, Alexander V.

doi:10.1109/ijcnn.2009.5179043

Cited by 68 publications

(36 citation statements)

References 21 publications

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“…Running the software specification on conventional supercomputers is out of the question due to high power consumption [5]. Commodity chips, which include DSP [6], GPU [7], and FPGA [8] solutions, also lead to relatively high power that limits scaling. Specifically, these solutions require high-bandwidth to communicate spikes from separately located processing and memory, and to meet real-time performance clock speeds are typically run in the gigahertz range.…”

Section: Introductionmentioning

confidence: 99%

Building block of a programmable neuromorphic substrate: A digital neurosynaptic core

Arthur

Merolla

Akopyan

et al. 2012

The 2012 International Joint Conference on Neural Networks (IJCNN)

109

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Abstract-The grand challenge of neuromorphic computation is to develop a flexible brain-like architecture capable of a wide array of real-time applications, while striving towards the ultra-low power consumption and compact size of biological neural systems. To this end, we fabricated a key building block of a modular neuromorphic architecture, a neurosynaptic core. Our implementation consists of 256 integrate-and-fire neurons and a 1,024×256 SRAM crossbar memory for synapses that fits in 4.2mm 2 using a 45nm SOI process and consumes just 45pJ per spike. The core is fully configurable in terms of neuron parameters, axon types, and synapse states and its fully digital implementation achieves one-to-one correspondence with software simulation models. One-to-one correspondence allows us to introduce an abstract neural programming model for our chip, a contract guaranteeing that any application developed in software functions identically in hardware. This contract allows us to rapidly test and map applications from control, machine vision, and classification. To demonstrate, we present four test cases (i) a robot driving in a virtual environment, (ii) the classic game of pong, (iii) visual digit recognition and (iv) an autoassociative memory.

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Section: Introductionmentioning

confidence: 99%

Building block of a programmable neuromorphic substrate: A digital neurosynaptic core

Arthur

Merolla

Akopyan

et al. 2012

The 2012 International Joint Conference on Neural Networks (IJCNN)

109

View full text Add to dashboard Cite

show abstract

“…In recent years, a large number of applications have used GPUs to speed up processing of neural networks algorithms [57][58][59][60][61] applied to various computer vision problems such as: representation and tracking of objects in scenes [62], face representation and tracking [63] or pose estimation [64].…”

Section: Gpgpu Architecturementioning

confidence: 99%

Real time motion estimation using a neural architecture implemented on GPUs

García-Rodríguez

Orts-Escolano

Angelopoulou

et al. 2014

J Real-Time Image Proc

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This work describes a neural network based architecture that represents and estimates object motion in videos. This architecture addresses multiple computer vision tasks such as image segmentation, object representation or characterization, motion analysis and tracking. The use of a neural network architecture allows for the simultaneous estimation of global and local motion and the representation of deformable objects. This architecture also avoids the problem of finding corresponding features while tracking moving objects. Due to the parallel nature of neural networks, the architecture has been implemented on GPUs that allows the system to meet a set of requirements such as: time constraints management, robustness, high processing speed and re-configurability. Experiments are presented that demonstrate the validity of our architecture to solve problems of mobile agents tracking and motion analysis.

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“…Large-scale implementations of Izhikevich neurons have been previously implemented in software, using computing clusters consisting of high-performance/high-powerconsuming general purpose processors [12], lower power fixed-point processors [13], FPGAs [14] and GPUs [15].…”

Section: Design Considerationsmentioning

confidence: 99%

Neural spiking dynamics in asynchronous digital circuits

Imam

Wecker

Tse

et al. 2013

The 2013 International Joint Conference on Neural Networks (IJCNN)

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Abstract-We implement a digital neuron in silicon using delay-insensitive asynchronous circuits. Our design numerically solves the Izhikevich equations with a fixed-point number representation, resulting in a compact and energy-efficient neuron with a variety of dynamical characteristics. A digital implementation results in stable, reliable and highly programmable circuits, while an asynchronous design style leads to energy-efficient clockless neurons and their networks that mimic the event-driven nature of biological nervous systems. In 65 nm CMOS technology at 1 V operating voltage and a 16-bit word length, our neuron can update its state 11,600 times per millisecond while consuming 0.5 nJ per update. The design occupies 29,500 µm 2 and can be used to construct dense neuromorphic systems. Our neuron exhibits the full repertoire of spiking features seen in biological neurons, resulting in a range of computational properties that can be used in artificial systems running neural-inspired algorithms, in neural prosthetic devices, and in accelerated brain simulations.

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Efficient simulation of large-scale Spiking Neural Networks using CUDA graphics processors

Cited by 68 publications

References 21 publications

Building block of a programmable neuromorphic substrate: A digital neurosynaptic core

Building block of a programmable neuromorphic substrate: A digital neurosynaptic core

Real time motion estimation using a neural architecture implemented on GPUs

Neural spiking dynamics in asynchronous digital circuits

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