Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders

Lin, Jun; Wang, Zhongfeng; Li, Li; Sha, Jian; Gao, Minglun

doi:10.1109/tcsii.2009.2015353

Cited by 25 publications

(17 citation statements)

References 11 publications

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“…The existing schemes to implement switch networks include the MS-CS network [20] and Benes network [13,21,22]. The former structure can handle the case when S is not a power of 2, while the latter is proved more efficient in area and gate count.…”

Section: The Reconfigurable Switch Networkmentioning

confidence: 99%

“…The former structure can handle the case when S is not a power of 2, while the latter is proved more efficient in area and gate count. In [13], the most efficient on-the-fly generation method of control signals is proposed. Therefore, we adopt the Benes network proposed in [13] for our decoder.…”

Section: The Reconfigurable Switch Networkmentioning

confidence: 99%

“…In [13], the most efficient on-the-fly generation method of control signals is proposed. Therefore, we adopt the Benes network proposed in [13] for our decoder. The structure is shown in Figure 7 and the features is given in Table 1.…”

Section: The Reconfigurable Switch Networkmentioning

confidence: 99%

“…Next, the hardware pipeline of the selected codes are optimized by the ant colony optimization (ACO) based scheduling algorithm, which can reduce much of the memory conflicts. Finally, detailed implementation schemes are proposed, i.e., reconfigurable switch network (adopted by [13]), offset-threshold decoding, split-row MMSA core, early-stoping scheme and multi-block scheme, and the corresponding multi-mode high-throughput decoder of the optimized codes is implemented on FPGA. The novelties of the proposed methodology are listed as follows:…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Systematic construction, verification and implementation methodology for LDPC codes

Cui

Wang

et al. 2012

J Wireless Com Network

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In this article, a novel and systematic Low-density parity-check (LDPC) code construction, verification and implementation methodology is proposed. The methodology is composed by the simulated annealing based LDPC code constructor, the GPU based high-speed code selector, the ant colony optimization based pipeline scheduler and the FPGA-based hardware implementer. Compared to the traditional ways, this methodology enables us to construct both decoding-performance-aware and hardware-efficiency-aware LDPC codes in a short time. Simulation results show that the generated codes have much less cycles (length 6 cycles eliminated) and memory conflicts (75% reduction on idle clocks), while having no BER performance loss compared to WiMAX codes. Additionally, the simulation speeds up by 490 times under float precision against CPU and a net throughput 24.5 Mbps is achieved. Finally, a net throughput 1.2 Gbps (bit-throughput 2.4 Gbps) multi-mode LDPC decoder is implemented on FPGA, with completely on-the-fly configurations and less than 0.2 dB BER performance loss.

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Section: The Reconfigurable Switch Networkmentioning

confidence: 99%

Section: The Reconfigurable Switch Networkmentioning

confidence: 99%

Section: The Reconfigurable Switch Networkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Systematic construction, verification and implementation methodology for LDPC codes

Cui

Wang

et al. 2012

J Wireless Com Network

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“…Typically, one-input one-output processing units are used to process the messages serially. The barrel shifter [29] is quite expensive and researchers [29], [30] have explored efficient implementations of the barrel shifter using Benes network structure. By mapping messages in this way, it is very efficient to implement highly flexible decoder for multiple standards [31], [32].…”

Section: Related Workmentioning

confidence: 99%

Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders

Chen

Kang

Lin

et al. 2011

IEEE Trans. Circuits Syst. I

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Abstract-Designers are increasingly relying on field-programmable gate array (FPGA)-based emulation to evaluate the performance of low-density parity-check (LDPC) codes empirically down to bit-error rates of 10 12 and below. This requires decoding architectures that can take advantage of the unique characteristics of a modern FPGA to maximize the decoding throughput. This paper presents two specific optimizations called vectorization and folding to take advantage of the configurable data-width and depth of embedded memory in an FPGA to improve the throughput of a decoder for quasi-cyclic LDPC codes. With folding it is shown that quasi-cyclic LDPC codes with a very large number of circulants can be implemented on FPGAs with a small number of embedded memory blocks. A synthesis tool called QCSyn is described, which takes the H matrix of a quasi-cyclic LDPC code and the resource characteristics of an FPGA and automatically synthesizes a vector or folded architecture that maximizes the decoding throughput for the code on the given FPGA by selecting the appropriate degree of folding and/or vectorization. This helps not only in reducing the design time to create a decoder but also in quickly retargeting the implementation to a different (perhaps new) FPGA or a different emulation board.Index Terms-Alignment, field programmable logic array (FPGA), folding, low-density parity-check (LDPC) decoder, memory system optimization, normalized min-sum algorithm, quasi-cyclic low-density parity-check (QC-LDPC) codes, very large scale integration (VLSI) implementation.

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A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders

Baas

2010

J Sign Process Syst

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A Split decoding algorithm is proposed which divides each row of the parity check matrix into two or multiple nearly-independent simplified partitions. The proposed method significantly reduces the wire interconnect and decoder complexity and therefore results in fast, small, and high energy efficiency circuits. Three full-parallel decoder chips for a (2048, 1723) LDPC code compliant with the 10GBASE-T standard using MinSum normalized, MinSum Split-2, and MinSum Split-4 methods are designed in 65 nm, seven metal layer CMOS. The Split-4 decoder occupies 6.1 mm 2 , operates at 146 MHz, delivers 19.9 Gbps throughput, with 15 decoding iterations. At 0.79 V, it operates at 47 MHz, delivers 6.4 Gbps and dissipates 226 mW. Compared to MinSum normalized, the Split-4 decoder chip is 3.3 times smaller, has a clock rate and throughput 2.5 times higher, is 2.5 times more energy efficient, and has an error performance degradation of 0.55 dB with 15 iterations.Keywords Low density parity check · LDPC · Iterative decoder · Split-Row · CMOS · 65 nm · 10GBASE-T · VLSI

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Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders

Cited by 25 publications

References 11 publications

Systematic construction, verification and implementation methodology for LDPC codes

Systematic construction, verification and implementation methodology for LDPC codes

Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders

A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders

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