A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders

Abstract

A Split decoding algorithm is proposed which divides each row of the parity check matrix into two or multiple nearly-independent simplified partitions. The proposed method significantly reduces the wire interconnect and decoder complexity and therefore results in fast, small, and high energy efficiency circuits. Three full-parallel decoder chips for a (2048, 1723) LDPC code compliant with the 10GBASE-T standard using MinSum normalized, MinSum Split-2, and MinSum Split-4 methods are designed in 65 nm, seven metal layer CMOS. The Split-4 decoder occupies 6.1 mm 2 , operates at 146 MHz, delivers 19.9 Gbps throughput, with 15 decoding iterations. At 0.79 V, it operates at 47 MHz, delivers 6.4 Gbps and dissipates 226 mW. Compared to MinSum normalized, the Split-4 decoder chip is 3.3 times smaller, has a clock rate and throughput 2.5 times higher, is 2.5 times more energy efficient, and has an error performance degradation of 0.55 dB with 15 iterations.Keywords Low density parity check · LDPC · Iterative decoder · Split-Row · CMOS · 65 nm · 10GBASE-T · VLSI

LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

“…To improve their efficiency, previous research has focused on reducing routing congestion and wire delay of the full parallel decoder implementations through bit-serial communication [13], wire partitioning [16], and algorithm modification [17]. A full parallel design using the Split-Row algorithm modification resulted in an implemented architecture that achieved 14 TOPS per Watt, that is, 10× the efficiency of a partial parallel decoder [14].…”

LDPC decoder area, timing, and energy models for early quantitative hardware cost estimates

“…2 the swaps are realized at the output of the minimum search and the output of the bit node. Recently, it was stated that it is "still challenging to fairly compare" decoders for different LDPC codes as the three basic metrics throughput, energy, and silicon area are "unfortunately complex functions" of the code parameters [5]. Therefore, it is customary to assume e.g.…”

“…Therefore, it is customary to assume e.g. a linear scaling of the decoder area with the block length n [4], [5]. Even more worse the energy per bit and iteration is assumed to be constant for various LDPC codes as it is not scaled with respect to code complexity.…”

Diseño de decodificadores de altas prestaciones para código LDPC

“…Las arquitecturas que se encuentran en la literatura se pueden clasificar, de acuerdo a la forma en la que se realizan las actualizaciones, en dos grandes grupos: paralelas [25,26,[31][32][33][34][35][36][37] y parcialmente paralelas [29,[38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54]. En las arquitecturas paralelas los procesos de actualización horizontal y vertical se realizan de forma concurrente, por lo que son necesarias tantas unidades CNP como filas tiene la matriz de paridad y tantas unidades VNP como columnas.…”

“…Con este método es necesario modificar el algoritmo de decodificación e introduce pérdidas en las prestaciones, sin embargo, las tasas de decodificación alcanzadas son altas y elárea se reduce considerablemente. Con el fin de mejorar las prestaciones, los mismos autores proponen varias modificaciones en [26,32,34,35,37]. En la arquitectura Sliced Message Passing -SMP, propuesta en [38], también se divide la matriz de paridad en bloques de columnas, pero a diferencia de la arquitectura Split-Row, enésta el procesado se hace de forma secuencial por bloques (parcialmente paralelo).…”