Efficient sequential consistency via conflict ordering

Lin, Changhui; Nagarajan, Vijay; Gupta, Rajiv; Rajaram, Bharghava

doi:10.1145/2150976.2151006

Cited by 61 publications

(9 citation statements)

References 37 publications

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“…Under the sequential consistency (SC) memory model, operations appear to interleave in an order respecting program order [29]. Providing end-to-end SC involves limiting memory access reordering by both the compiler and hardware, which slows programs and/or relies on custom hardware support [1,32,33,41,47,51,53,55]…”

Section: Background and Motivationmentioning

confidence: 99%

Hybrid Static–Dynamic Analysis for Statically Bounded Region Serializability

et al. 2015

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Data races are common. They are difficult to detect, avoid, or eliminate, and programmers sometimes introduce them intentionally. However, shared-memory programs with data races have unexpected, erroneous behaviors. Intentional and unintentional data races lead to atomicity and sequential consistency (SC) violations, and they make it more difficult to understand, test, and verify software. Existing approaches for providing stronger guarantees for racy executions add high run-time overhead and/or rely on custom hardware. This paper shows how to provide stronger semantics for racy programs while providing relatively good performance on commodity systems. A novel hybrid static--dynamic analysis called \emph{EnfoRSer} provides end-to-end support for a memory model called \emph{statically bounded region serializability} (SBRS) that is not only stronger than weak memory models but is strictly stronger than SC. EnfoRSer uses static compiler analysis to transform regions, and dynamic analysis to detect and resolve conflicts at run time. By demonstrating commodity support for a reasonably strong memory model with reasonable overheads, we show its potential as an always-on execution model.

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Section: Background and Motivationmentioning

confidence: 99%

Hybrid Static–Dynamic Analysis for Statically Bounded Region Serializability

et al. 2015

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“…OmniOrder is the first scheme that allows these atomic blocks to provide speculative data to other processors. Other schemes retain SC without needing out-of-window speculation -e.g., Conflict Ordering [17] tries to avoid dependence cycles that could violate SC, while End-to-End SC [23] directs accesses to private and shared (or unsafe) data to different write buffers, and only reorders the former.…”

Section: Related Workmentioning

confidence: 99%

OmniOrder: Directory-based conflict serialization of transactions

Qian¹,

Sahelices²,

Torrellas³

2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

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Effective execution of atomic blocks of instructions (also called transactions) can enhance the performance and programmability of multiprocessors. Atomic blocks can be demarcated in software as in Transactional Memory (TM) or dynamically generated by the hardware as in aggressive implementations of strict memory consistency. In most current designs, when two atomic blocks conflict, one is squashed -a performance loss that is often unnecessary.To avoid this waste, this paper presents OmniOrder, the first design that efficiently executes conflicting atomic blocks concurrently in a directory-based coherence environment. The idea is to keep only non-speculative data in the caches and, when the cache coherence protocol transfers a line, include in the message the history of speculative updates to the line. The coherence protocol transitions are unmodified. We evaluate OmniOrder with 64-core simulations. In a TM environment, OmniOrder reduces the execution time of the STAMP applications by an average of 18.4% over a scheme that squashes on conflict. In an environment with SC enforcement with speculation, we run 11 programs that implement concurrent algorithms. OmniOrder reduces the programs' execution time by an average of 15.3% relative to a scheme that squashes on conflict. Finally, OmniOrder's communication overhead of transferring the history of speculative updates is negligible.

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“…This requires fairly complex hardware that keeps track of the register and memory state before each committed load, detects potential SC violations by comparing incoming coherence invalidation requests with the addresses of committed loads, and performs a rollback when a potential SC violation is detected. To avoid speculation, Lin et al [38] proposed to check if there is any conflict with pending accesses in remote cores before committing a memory instruction from the ROB. While this design eliminates the need for out-of-window checkpoint and rollback support, it still requires significant changes to the coherence protocol to efficiently perform conflict detection before committing a memory instruction from the ROB.…”

Section: Efficient and Complexity-effective Sc Hardwarementioning

confidence: 99%