Efficient realization of digital logic circuit using QCA multiplexer

Goswami, Mrinal; Kumar, B. Dilli; Tibrewal, Harsh; Mazumdar, Subhra

doi:10.1109/icbim.2014.6970972

Cited by 32 publications

(27 citation statements)

References 6 publications

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“…This design is further extended to realize a 2:1 multiplexer and its latency, area and energy dissipation parameters are discussed. The multiplexer architectures in [1] and [3] are improved using the same co planar approach. The designs previously discussed were not efficient enough and hence it was improved by reducing the cell count which in turn reduced area and energy dissipated.…”

Section: Literature Reviewmentioning

confidence: 99%

“…The conventional D flip-flop architecture was referred having 30 cells in [3], 19 cells in [4] and 21 cells in [6]. These complex architectures were found to be inefficient when implemented on a large scale.…”

Section: Literature Reviewmentioning

confidence: 99%

“…Thus, by integrating them, implementation at nano scale level can be achieved. The designed architecture is compared with the architecture in [3] which consists of 72 cells and the architecture in [6] which consists of 40 cells. The existing architecture is of lesser efficiency in terms of speed and energy consumption.…”

Section: Literature Reviewmentioning

confidence: 99%

“…Hence, QCA is the best alternative available for CMOS technology. The present CMOS based architecture consumes high power which inhibits energy efficient realization of complex circuits at nanoscale [3]. Hence, for attaining a higher computational power and for obtaining a dense circuit, QCA is the best alternative available.…”

Section: Introductionmentioning

confidence: 99%

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A Novel QCA based Compact Scan Flip-flop for Digital Design Testing

S.,

T.N.,

B.S.

2019

IJEAT

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Quantum-dot Cellular Automata (QCA) is an emerging technology used for computation at nano scale. It is an excellent alternative for the conventional CMOS technology. QCA provides us with low energy, high speed, faster switching speed and compact structures for logical circuits. Testing is the integral part of the design verification, scan flip-flop is used for device testing. It is used in processors for a built-in self-test. The objective of this paper is to design an optimized structure of a scan flip-flop which occupies less area and dissipates minimum energy compared to the previously designed architectures. The efficiency of the proposed structure is analyzed in terms of cell count, energy dissipation, and area occupied by the logical circuit. Proposed scan flip flop has a cell count of 32 and an energy dissipation of 0.0105 eV which is 20 % more efficient in terms of cell count and 29 % more efficient than the previous designs. The CAD tool, QCADesigner is used for design and simulation. Cells have a dimension of 18 nm in height and 18 nm in breadth and there is a distance of 2 nm between these cells. Bi-stable and coherence vector simulation engines are used in the tool for simulation.

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Section: Literature Reviewmentioning

confidence: 99%

Section: Literature Reviewmentioning

confidence: 99%

Section: Literature Reviewmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Novel QCA based Compact Scan Flip-flop for Digital Design Testing

S.,

T.N.,

B.S.

2019

IJEAT

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“…QCA uses the arrangement of intracellular electrons for binary representation instead of voltage level, so there is flow of current in this technique [3][4][5]. Many efforts have been made to implement the crucial components in logic circuits such as XOR [6][7][8][9][10][11] and multiplexer [12][13][14][15][16][17][18] using this nanotechnology. The multiplexer (MUX) was extensively utilized to implement many digital circuits such as RAM cells and ALU.…”

Section: Introductionmentioning

confidence: 99%

Optimum multiplexer design in quantum-dot cellular automata

Alkaldy

Majeed

Zainal

et al. 2020

IJEECS

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Quantum-dot Cellular Automata (QCA) is one of the most important computing technologies for the future and will be the alternative candidate for current CMOS technology. QCA is attracting a lot of researchers due to many features such as high speed, small size, and low power consumption. QCA has two main building blocks (majority gate and inverter) used for design any Boolean function. QCA also has an inherent capability that used to design many important gates such as XOR and Multiplexer in optimal form without following any Boolean function. This paper presents a novel design 2:1 QCA-Multiplexer in two forms. The proposed design is very simple, highly efficient and can be used to produce many logical functions. The proposed design output comes from the inherent capabilities of quantum technology. New 4:1 QCA-Multiplexer has been built using the proposed structure. The output waveforms showed the wonderful performance of the proposed design in terms of the number of cells, area, and latency.

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Novel multilayer SISO shift register architecture in QCA technology and its usage in communications

Divshali

Rezai

Karimi

2022

Int J Communication

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Summary The QCA technology is a promising emerging technology at nano‐scale for replacing CMOS technology. Shift register has a vital role in communication networks and digital electronic circuits that are the main components of integrated circuits and memory. In this study, novel and efficient delay circuit (pseudo‐D‐Latch) is designed. Then, 3‐, 4‐, and 5‐bit SISO QCA shift register architectures are developed and evaluated in single layer, 3‐layer and 5‐layer using the designed delay circuit. The designed architectures are evaluated using QCADesigner‐E tool version 2.2. The results demonstrate that the pseudo‐D‐Latch circuit contains 17 cells and 0.01 μm2 area. The 3‐, 4‐, and 5‐bit single layer SISO QCA shift register architecture contains 63 (0.05 μm2), 85 (0.66 μm2), and 107 (0.08 μm2) cells (area), respectively. The 3‐ and 4‐bit 3‐layer SISO QCA shift register architecture contains 63 (0.03 μm2) and 84 (0.03 μm2) cells (area), respectively. The 3‐ and 5‐bit 5‐layer SISO QCA shift register architecture contains 62 (0.02 μm2) and 105 (0.032 μm2) cells (area), respectively. These results show that the designed QCA architectures provide improvements compared with other SISO QCA architectures.

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Efficient realization of digital logic circuit using QCA multiplexer

Cited by 32 publications

References 6 publications

A Novel QCA based Compact Scan Flip-flop for Digital Design Testing

A Novel QCA based Compact Scan Flip-flop for Digital Design Testing

Optimum multiplexer design in quantum-dot cellular automata

Novel multilayer SISO shift register architecture in QCA technology and its usage in communications

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