Efficient Real-Time Digital Subcarrier Cross-Connect (DSXC) Based on Distributed Arithmetic DSP Algorithm

Xu, Tao; Fumagalli, Andrea; Hui, Rongqing

doi:10.1109/jlt.2019.2937787

Cited by 7 publications

(1 citation statement)

References 18 publications

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“…In the in-memory computing for emerging memory devices, there is no separation between memory and logic, to overcome Von-Neumann bottleneck and also in-memory computing devices are designed with zero-off state power and due to this, they have a distinct advantage of the non-volatile state [8]. The in-memory computing is combined with a high gate or synapse density which enables forming of cross-bar array in the device, which can be easily integrated with CMOS with high density, operating with high current and voltage consuming high dynamic power, with Inmemory computing device contains long switching time hence they operate with limited speed and have limited endurance, again the cross-bar in-memory computing is highly parallel, operate with low-power, low cost [9]. The verticals of Cross-bar inmemory computing are bio-inspired computing, deep learning, inmemory logic, chip/data security, architecture, device modeling [10].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Reconfigurable Neuro-Inspired Computing Model on a FPGA

Prashanth¹,

Ahmed²

2020

Adv. sci. technol. eng. syst. j.

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In this paper we design a large scale reconfigurable digital bio-inspired computing model. We consider the reconfigurable and event driven parameters in the developed fieldprogrammable neuromorphic computing system. The various Intellectual Property (IP) cores are developed for the modules such as Block RAM, Differential Clock, Floating Point, and First In First Out (FIFO) for the design of the neuron model in Xilinx ISE, with exploration of register transfer logic (RTL) and hardware synthesis using Verilog code. The architecture for design at device level offers the best possible design tradeoff for specific processor architectures and development choices. In this paper we perform algorithmic design of a large scale reconfigurable logical bio-inspired computing model. The proposed algorithm is implemented on Field Programmable Gate Array (FPGA) to develop a neuron model to be utilized in neuromorphic computing system.

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Section: Introductionmentioning

confidence: 99%