Efficient processor support for DRFx, a memory model with exceptions

Abstract

A longstanding challenge of shared-memory concurrency is to provide a memory model that allows for efficient implementation while providing strong and simple guarantees to programmers. The C++0x and Java memory models admit a wide variety of compiler and hardware optimizations and provide sequentially consistent (SC) semantics for data-race-free programs. However, they either do not provide any semantics (C++0x) or provide a hard-tounderstand semantics (Java) for racy programs, compromising the safety and debuggability of such programs. In earlier work we proposed the DRFx memory model, which addresses this problem by dynamically detecting potential violations of SC due to the interaction of compiler or hardware optimizations with data races and halting execution upon detection. In this paper, we present a detailed micro-architecture design for supporting the DRFx memory model, formalize the design and prove its correctness, and evaluate the design using a hardware simulator. We describe a set of DRFx-compliant complexity-effective optimizations which allow us to attain performance close to that of TSO (Total Store Model) and DRF0 while providing strong guarantees for all programs.

Peacenik

“…Researchers have proposed systems that provide fail-stop semantics by generating a consistency exception upon a data race [19,21,24,49,53,67]. Since sound and precise dynamic race detection is expensive [19,24], efficient systems provide fail-stop consistency by detecting conflicts between concurrently executing synchronization-free regions (SFRs) [9,10,25,41,44,60]. (An SFR is a sequence of per-thread dynamic instructions demarcated by synchronization operations.)…”

“…Alternatively, instead of restricting optimizations, a system can detect the conditions for weak or undefined semantics and treat them as fail-stop errors [9,10,21,25,41,44,53,60,67]. Under fail-stop memory consistency, all programs have well-defined behavior, and an execution stops if it might have undefined behavior due to a data race.…”

Accelerating sequential consistency for Java with speculative compilation

“…These approaches are implemented in the Jikes research virtual machine [3] and evaluated only on x86. Work on region serializability for C has achieved good performance either through special-purpose hardware [21,24,36] or by requiring 2N cores to execute an application with N threads [27].…”

Efficient sequential consistency via conflict ordering

“…To redress this there have been works that employ dynamic race detection [9] in order to stop execution when semantics become undefined. Since dynamic data race detection can be slow, recent works [21,22,30] propose raising an exception upon encountering an SC violation as this can be done more efficiently.…”