Efficient Partial-Parallel Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes

Zhang, Xinmiao; Cai, Fang

doi:10.1109/tcsi.2010.2071830

Cited by 55 publications

(24 citation statements)

References 16 publications

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“…We also indicate if the results are post-synthesis or estimated, if the results are only for a part of the architecture, and the technology used. Despite the implementation results shown in Table 2, where the algorithms in [13] and [14] seem to be more efficient than the algorithm in [9], in [9] it is shown that this is more efficient in terms of throughput over area ratio than the previous work of the same authors [11][12][13][14][15]. On the other hand, the recent architecture proposed in [4], which has lower throughput over area ratio than [9], has introduced other advantages such as a configurable architecture.…”

Section: Comparison With Existing Architecturesmentioning

confidence: 83%

Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes

García-Herrero

Canet

Valls

2012

Circuits Syst Signal Process

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A VLSI architecture for the generalized bit-flipping decoding algorithm for non-binary low-density parity-check codes is proposed in this paper. The tentative decoding steps of the algorithm have been modified to avoid computing and storing a matrix of dimension N × 2 q , for a code (N, K) over GF(2 q ), reducing its complexity with a minimal penalization of its performance, less than 0.05 dB compared with the original algorithm. The architecture was synthesized using a 90 nm standard cell library, for the (837, 723) non-binary code over GF(2 5 ), requiring 590220 xor gates and achieving a throughput of 89 Mbps. Additionally, it was implemented in a Virtex-VI FPGA device with a cost of 4070 slices and a throughput of 44.6 Mbps.

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Section: Comparison With Existing Architecturesmentioning

confidence: 83%

Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes

García-Herrero

Canet

Valls

2012

Circuits Syst Signal Process

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“…Table 1 summarizes the hardware requirements and performance of the proposed decoder and also other partially-parallel decoders reported in the literature. Among the partially-parallel decoder architectures reviewed [27][28][29][30][31][32][33][34][35][36][37][38][39], only those implemented on Xilinx Virtex 4 and Virtex 5 FPGA are listed in Table 1. Although Virtex 5 has performance advantage over Virtex 4, the decoders implemented on the former device [38,39] require comparatively more resources and also achieve substantially less throughput than the proposed decoder on Virtex 4 FPGA.…”

Section: Analysis Of Implementation Resultsmentioning

confidence: 99%

Resource efficient LDPC decoders for multimedia communication

Chandrasetty

Aziz

2015

Integration

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a b s t r a c tAchieving high image quality is an important aspect in an increasing number of wireless multimedia applications. These applications require resource efficient error correction hardware to detect and correct errors introduced by the communication channel. This paper presents an innovative flexible architecture for error correction using Low-Density Parity-Check (LDPC) codes. The proposed partiallyparallel decoder architecture utilizes a novel code construction technique based on multi-level Hierarchical Quasi-Cyclic (HQC) matrix. The proposed architecture is resource efficient, provides scalable throughput and requires substantially less power compared to other decoders reported to date. The proposed decoder has been implemented on a Xilinx FPGA suitable for WiMAX application and achieves a throughput of 548 Mbps. Performance evaluation of the decoder has been carried out by transmitting JPEG images over a wireless noisy channel and comparing the quality of the reconstructed images with those from other similar decoders.

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“…Decoding gain over MS 0.5dB 0 0 * Here REG indicates 1-bit register. † 1-bit REG is converted to three 2-input XOR according to [22]. ‡ Hardware efficiency is the ratio of throughput to total gate count.…”

Section: Peformance Anaylsis and Comparsionmentioning

confidence: 99%

Architecture optimizations for BP polar decoders

Yuan

Parhi

2013

2013 IEEE International Conference on Acoustics, Speech and Signal Processing

100

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Polar codes have emerged as important channel codes because of their capacity-achieving property. For low-complexity polar decoding, hardware architectures for successive cancellation (SC) algorithm have been investigated in prior works. However, belief propagation (BP)-based architectures have not been explored in detail. This paper begins with a review of min-sum (MS) approximated BP algorithm, and then proposes a scaled MS (SMS) algorithm with improved decoding performance. Then, in order to solve long critical path problem in the SMS algorithm, we propose an efficient critical path reduction approach. Due to its generality, this optimization method can be applied to both of SMS and MS algorithms. Compared with the state-of-the-art MS decoder, the proposed (1024, 512) SMS design can lead to 0.5dB extra decoding gain with the same hardware performance. Besides, the proposed optimized MS architecture can also achieve more than 30% and 80% increase in throughput and hardware efficiency, respectively.

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Efficient Partial-Parallel Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes

Cited by 55 publications

References 16 publications

Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes

Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes

Resource efficient LDPC decoders for multimedia communication

Architecture optimizations for BP polar decoders

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