Efficient mitigation of data and control flow errors in microprocessors

Parra, Luis; Lindoso, Almudena; Portela, M.; Entrena, Luis; Restrepo-Calle, Felipe; Cuenca-Asensi, Sergio; Martínez-Álvarez, Antonio

doi:10.1109/radecs.2013.6937381

Cited by 10 publications

(15 citation statements)

References 25 publications

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“…In [28], Meixner and Sorin have done CFC in software and redundancy on hardware by duplicating the hardware modules. In [29], Parra et al have done the reverse. An additional hardware module is used to check the CFC and redundancy is done at the software level.…”

Section: Related Workmentioning

confidence: 99%

Soft‐error reliable architecture for future microprocessors

Gopalakrishnan

Singh

2019

IET Computers & Digital Techniques

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The transient error is the failure of the device due to transient hardware faults caused by high-energy particles like neutron and alpha particle strikes. In this study, the authors propose two schemes of fault-tolerant architecture. The first scheme is a hardware-based solution called REMO that combines the best features of space and time redundancy. REMO provides very high fault coverage with minimum overheads in performance, power and area. The second scheme, REMORA combines the best features of hardware and software approaches of fault tolerance. The persistent issue of unprotected code which exists in software approaches is eliminated in this proposal. Simulation results from a SPEC2006 benchmark suite indicate, REMO incurs an increase in the area of about 6%, power overhead is 9% in spite of redundant execution and a negligible performance penalty during a fault-free run. In REMORA, performance degradation increases to 12%. The code size inflation is close to 12%. This is due to the additional signature instructions inserted into the application program. In this study, the authors have explored the possibility of eliminating this penalty by embedding the signatures in control flow instructions. The power and area overhead of REMORA is on par with REMO.

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Section: Related Workmentioning

confidence: 99%

Soft‐error reliable architecture for future microprocessors

Gopalakrishnan

Singh

2019

IET Computers & Digital Techniques

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“…Other approaches have been proposed that make a more elaborated use of the trace information. In [23], a hybrid technique is proposed using the trace interface to harden the execution flow while data errors are handled with SWIFT-R technique. A new technique was proposed in [6] that compares the program flow information retrieved from two different points: the trace interface and the memory bus.…”

Section: Related Workmentioning

confidence: 99%

PTM-based hybrid error-detection architecture for ARM microprocessors

Pena-Fernandez

Lindoso

Entrena

et al. 2018

Microelectronics Reliability

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This work presents a hybrid error detection architecture that uses ARM PTM trace interface to observe ARM microprocessor behaviour. The proposed approach is suitable for COTS microprocessors because it does not modify the microprocessor architecture and is able to detect errors thanks to the reuse of its trace subsystem. Validation has been performed by proton irradiation and fault injection campaigns on a Zynq AP SoC including a Cortex-A9 ARM microprocessor and an implementation of the proposed hardware monitor in programmable logic. Experimental results demonstrate that a high error detection rate can be achieved on a commercial microprocessor.

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“…The CFEs detection technology can be divided into hardware-based methods [8][9][10], mixed software-hardware methods [11][12][13], and software-based control flow detection technology. The former requires additional hardware components to detect CFEs.…”

Section: Introductionmentioning

confidence: 99%

A Configurable Software-based Approach for Detecting CFEs Caused by Transient Faults

2021

KSII TIIS

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Transient faults occur in computation units of a processor, which can cause control flow errors (CFEs) and compromise system reliability. The software-based methods perform illegal control flow detection by inserting redundant instructions and monitoring signature. However, the existing methods not only have drawbacks in terms of performance overhead, but also lack of configurability. We propose a configurable approach CCFCA for detecting CFEs. The configurability of CCFCA is implemented by analyzing the criticality of each region and tuning the detecting granularity. For critical regions, program blocks are divided according to space-time overhead and reliability constraints, so that protection intensity can be configured flexibly. For other regions, signature detection algorithms are only used in the first basic block and last basic block. This helps to improve the fault-tolerant efficiency of the CCFCA. At the same time, CCFCA also has the function of solving confusion and instruction self-detection. Our experimental results show that CCFCA incurs only 10.61% performance overhead on average for several C benchmark program and the average undetected error rate is only 9.29%. CCFCA has high error coverage and low overhead compared with similar algorithms. This helps to meet different cost requirements and reliability requirements.

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Efficient mitigation of data and control flow errors in microprocessors

Cited by 10 publications

References 25 publications

Soft‐error reliable architecture for future microprocessors

Soft‐error reliable architecture for future microprocessors

PTM-based hybrid error-detection architecture for ARM microprocessors

A Configurable Software-based Approach for Detecting CFEs Caused by Transient Faults

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