Efficient key-dependent message authentication in reconfigurable hardware

Abstract

The paper presents a novel concept of processor aimed at symmetric-key cryptographic applications. Its architecture is optimized for implementation of common cryptography tasks. The processor has 128-bit separated data and key registers, dedicated instruction set optimized for key generation and management, embedded cipher, and embedded random number generator. From an architectural point of view, the most important characteristic of the proposed crypto-processor is the physical separation of data and key registers and buses, insuring that confidential keys will never leave the system in clear. This way, the processor enables to separate protected and unprotected security zones easily and also achieve complete physical isolation of key management and data zones inside the single FPGA. The first version of the processor implemented in Xilinx Virtex 5 FPGA device achieves the frequency of 160 MHz and it occupies 1343 configurable logic blocks and 21 embedded memory blocks.

AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations

“…In Algorithm 1, if H is fixed, the multiplier is called a fixed operand GF (2 128 ) multiplier as shown by [5]. This design proposed by [5] can be used efficiently (smaller area) on FPGAs as the circuit is specialized for H. We integrated this multiplier proposed by [5] with a key-synthesized AES engine in [6] in order to support slow changing key applications like Virtual Private Networks (VPNs).…”

“…This design proposed by [5] can be used efficiently (smaller area) on FPGAs as the circuit is specialized for H. We integrated this multiplier proposed by [5] with a key-synthesized AES engine in [6] in order to support slow changing key applications like Virtual Private Networks (VPNs). Also, in [6], we proposed a protocol to secure the FPGA reconfiguration to protect the bitstream because it is a key-based bitsream.…”

FPGA-Based High-Speed Authenticated Encryption System

“…Wang et al [18] presented a GHASH architecture based on four GHASH cores that achieved a throughput of 123.1 Gbit/s on a Virtex-5. Crenne et al [4] reached 238.1 Gbit/s by using 8 parallel finite-field multipliers, also targeting a Xilinx Virtex-5 FPGA. Since we aim at a full AE architecture, i.e., a design including both the authenticity and the confidentiality part, we do not consider these GHASH-only implementations for our investigations.…”

“…Although our development board and the AE cores have been designed to support a 100 Gbit/s communication, real-world experiments have so far only been undertaken using a 40 Gbit/s ciphertext interface due to financial reasons 4 . Nevertheless, measurements of the overall system proved it to be operational at data rates up to 40 Gbit/s with all the features described above.…”

Efficient AES-GCM for VPNs using FPGAs

“…The key used for encryption and authentication is synthesized into the module structure in order to reduce the consumed area. This is achieved by combining the GF(2 128 ) multiplier proposed by [6] with our presented AES.…”