Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC
DOI: 10.1109/edtc.1994.326816
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Efficient implementations of self-checking multiply and divide arrays

Abstract: ISBN: 0818654104In this paper we present efficient self checking implementations for multiply and divide arrays. These implementations are strongly fault secure or totally self-checking for a comprehensive fault model which includes stuck-at, stuck-on and stuck-open faults. They are compatible with data paths checked by the parity code (i.e. no code translators are needed), so that the self checking implementation of the whole data path is simplified

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Cited by 13 publications
(2 citation statements)
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“…The naive approach to computational error correction is TMR [86], requiring over a 200% overhead in area and energy for single error correcting capability. Several techniques in the form of arithmetic codes such as AN codes [6,18,19,41,66,88], self-checking [30,33,44,[48][49][50]84], and self-correcting [15,20,26,37,45,55,62,63,74,83] adders and multipliers have since been devised. Orthogonally, proposals employ redundancy at a higher granularity, such as timing speculation (wherein error correction capability is limited to circuit timing violations) [16,23], partial pipeline replication [2], or checkpoint-rollback-recovery such as those in IBM Power8 processors [29].…”
Section: Related Workmentioning
confidence: 99%
“…The naive approach to computational error correction is TMR [86], requiring over a 200% overhead in area and energy for single error correcting capability. Several techniques in the form of arithmetic codes such as AN codes [6,18,19,41,66,88], self-checking [30,33,44,[48][49][50]84], and self-correcting [15,20,26,37,45,55,62,63,74,83] adders and multipliers have since been devised. Orthogonally, proposals employ redundancy at a higher granularity, such as timing speculation (wherein error correction capability is limited to circuit timing violations) [16,23], partial pipeline replication [2], or checkpoint-rollback-recovery such as those in IBM Power8 processors [29].…”
Section: Related Workmentioning
confidence: 99%
“…Nikolaidis [13] propose efficient parity prediction techniques to achieve (detection only) low area overhead of 17% for carry lookahead adders. As noted by the residue based detection work of Pan et al [14], Nikolaidis et al propose [15] using differential logic circuits to implement each cell of array-based multipliers, and, also propose [16] output duplicated Booth multipliers, again, for detection alone. The latter was improved upon by Marienfeld et al [17] to achieve a hardware overhead of 35% for detection in 32 bit multipliers.…”
Section: Micro-architectural / Isa Independent Techniquesmentioning
confidence: 99%