Efficient Implementation of QR Decomposition for Gigabit MIMO-OFDM Systems

Huang, Zhiyong; Tsai, Pei–Yun

doi:10.1109/tcsi.2011.2123770

Cited by 103 publications

(73 citation statements)

References 17 publications

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“…In Fig. 8, the number of fractional bits is set to 13, while the total WL changes from The QRD architectures in [5,7,8,9] are based on GR algorithm, and [6,10] are based on Hybrid algorithm. Lin JS [5] proposed a two-phase QRD architecture, which incorporated a single exchange of the column and arrow into the general QRD procedure to achieve a better NR performance of 138.5 M. Zhang C [6] designed a hardware architecture based on hybrid GR algorithm to increase the parallelism, which achieves a good NR performance of 138 M and relatively low NPL of 87 ns.…”

Section: Implementation Results and Comparisonmentioning

confidence: 99%

“…As the Newton-Raphson iteration equation (8) is similar with (5) in scheme, the hardware for (5) can be reused to calculate (8). Therefore the Newton-Raphson iteration entails no more hardware overhead while increase accuracy.…”

Section: Classical Mgs Algorithmmentioning

confidence: 99%

“…The majority of QRD algorithms are mainly based on three original algorithms -Householder transformation (HT) algorithm [3], modified Gram-Schmidt (MGS) algorithm [4], and Givens rotation (GR) algorithm [5,6,7,8,9]. As the HT algorithm is too complex to be implemented in hardware, the existing QRD architectures are mainly based on GR algorithm and MGS algorithm in MIMO systems.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Low latency QRD algorithm for future communication

Chen

Liu

Wang

et al. 2017

IEICE Electron. Express

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QR decomposition (QRD) has been a vital component for various baseband processing algorithms, and is one potential bottleneck for next generation (5G) high-performance MIMO systems. To ulteriorly optimize the processing latency (PL) of QRD hardware architecture, this letter proposes a novel anticipated MGS (AMGS) algorithm based on conventional MGS algorithm. Anticipated computing is proposed in AMGS to diminish the PL. Moreover, Reciprocal square root (RSR) algorithm is designed to eliminate the complex operations (dividing and square root), making AMGS algorithm suit more for baseband processors. To evaluate the performance of the proposed AMGS algorithm, the corresponding triangular systolic array (TSA) hardware architecture is also implemented based on AMGS algorithm, whose working frequency is up to 417 MHz in 0.13 um CMOS technology to decompose a 4 × 4 real matrix in 31 clock cycles. The implementation results show that the PL performance is superior to other similar works of the literatures we know.

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Section: Implementation Results and Comparisonmentioning

confidence: 99%

Section: Classical Mgs Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low latency QRD algorithm for future communication

Chen

Liu

Wang

et al. 2017

IEICE Electron. Express

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“…Tree search based detectors prefer RVD due to the easy enumeration of possible child nodes [5]. Any matrix in C N ×N can be represented by an equivalent matrix in R 2N ×2N .…”

Section: B Complexity Reduction Due To Real Valued Decompositionmentioning

confidence: 99%

A high-speed QR decomposition processor for carrier-aggregated LTE-A downlink systems

Gangarajaiah

Liu

Stala

et al. 2013

2013 European Conference on Circuit Theory and Design (ECCTD)

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Abstract-This paper presents a high-speed QR decomposition (QRD) processor targeting the carrier-aggregated 4 × 4 Long Term Evolution-Advanced (LTE-A) receiver. The processor provides robustness in spatially correlated channels with reduced complexity by using modifications to the Householder transform, such as decomposing-target redefinition and matrix real-valued decomposition. In terms of hardware design, we extensively explore flexibilities in systolic architectures using a high-level synthesis tool to achieve area-power efficiency. In a 65 nm CMOS technology, the processor occupies a core area of 0.77 mm 2 and produces 72 MQRD per second, the highest reported throughput. The power consumed in the proposed processor is 127 mW.

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“…M ÞF M and apply QR decomposition to G M based on the modified Gram-Schmidt algorithm [15] . Thus, Eq.…”

mentioning

confidence: 99%

Experimental demonstration of indoor interfered visible light communication system employing successive interference cancellation

Li¹,

Li²,

Yang³

et al. 2017

中国光学快报

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Multipath interference induced power fading occurs when the transmission path lengths from the light emitting diodes to a single receiver are different in a visible light communication system. To solve this problem, we apply a QR-decomposition-based channel equalizer (QR-CE) to achieve successive interference cancellation for a discrete Fourier transform spreading (DFT-S) orthogonal frequency division multiplexing (OFDM) signal. We experimentally demonstrate a 200 Mb/s DFT-S OFDM over a 2 m free-space transmission. The experimental results show that a DFT-S OFDM with QR-CE attains much better bit error rate performance than a DFT-S OFDM with conventional CEs. The impacts of several parameters on a QR-CE are also investigated.

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Efficient Implementation of QR Decomposition for Gigabit MIMO-OFDM Systems

Cited by 103 publications

References 17 publications

Low latency QRD algorithm for future communication

Low latency QRD algorithm for future communication

A high-speed QR decomposition processor for carrier-aggregated LTE-A downlink systems

Experimental demonstration of indoor interfered visible light communication system employing successive interference cancellation

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