Efficient implementation of one and two dimensional digital signal processing algorithms on a multi-processor architecture

Barnwell, T.P.; Gaglio, Salvatore; Hodges, C.

doi:10.1109/icassp.1979.1170628

Cited by 3 publications

(6 citation statements)

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“…If this operation is performed entirely on one processor, then the multiplies and adds are not all performed simultaneously, but rather are performed in a specific sequence. It is therefore not true that (1) all the previous 10 values of the output need to be available before any arithmetic operations are performed.…”

Section: Implementation Of the Hr Filter Using Ssimdmentioning

confidence: 98%

“…The approach to automatic code generation for multiprocessor systems presented last year [1] requires three basic steps. First, the given DSP problem has to be broken down into a task or computation that is done repeatedly on different data.…”

Section: The Implementation Of An Lpc Speech Synthesizermentioning

confidence: 99%

“…The characteristics of this machine, along with an approach to automatic code generation for a large class of digital signal processing algorithms, oas presented last year at ICASSP [1]. This paper is divided into three parts.…”

Section: Introductionmentioning

confidence: 99%

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The implementation of an all digital speech synthesizer using a multimicroprocessor architecture

Hodges

Barnwell²,

McWhorter³

ICASSP '80. IEEE International Conference on Acoustics, Speech, and Signal Processing

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Section: Implementation Of the Hr Filter Using Ssimdmentioning

confidence: 98%

Section: The Implementation Of An Lpc Speech Synthesizermentioning

confidence: 99%

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The implementation of an all digital speech synthesizer using a multimicroprocessor architecture

Hodges

Barnwell²,

McWhorter³

ICASSP '80. IEEE International Conference on Acoustics, Speech, and Signal Processing

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“…The program is obtained by maximizing the minimum value of M(L). Third, and perhaps most important, the optimum time skew, t , is not a function of either (2) the program duration'or the number of recursive inputs or outputs of the program. This allows for several important generalizations to be made, and, for properly written programs, leads to very impressive solutions.…”

Section: Mark Randolphmentioning

confidence: 99%

Optimum implementation of single time index signal flow graphs on synceronous multiprocessor machines

Barnwell

Hodges²,

Randolph³

ICASSP '82. IEEE International Conference on Acoustics, Speech, and Signal Processing

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This paper summarizes the results of a theoretical and experimental study of a general technice for the implementation of recursive and nonrecursive signal flow graphs and other arithmetic algorithms on synchronous digital machines composed of many identical programmable processors. This technique can be characterized by two fundamental Jroperties. First, it uses the Skewed Single Instruction Multiple Data (SSIND) mode in which exactly the same program is executed on all the processors [1], and that program is exactly a single processor realization of the entire algorithm being implemented. Second, all the data precedence relations among the processors are automatically maintained by the inherent synchrony of the system. .]is often results in processor-optimum solutions which the use of 1 processors leads exactly to an 1 fold increase in the system throughput.In the final analyses, the techniques discussed here result in a procedure in which the algorithm is specified in some simple notation, such as a set of difference equations, and from this a completely parallel multiprocessor implementation for the algorithm is generated. The resulting Implementation is always either processor-optimum or tine-optimum in which the absolute throughput limit for the technique has been reached. In addition, for a large class of recursive signal flow graphs, the implementations are absolute-optimum in the sense that there is no other implementation for a particular signal flow graph and a particular constituent processor which ever leads to greater systems throughput. The techniques discussed here have been tested on a synchronous multiprocessor THE SSIND MODEThe fundamental computational mode which is utilized in these implementations is the Skewed Single Instruction Multiple Data Mode. In this tnode, exactly the same instruction stream is executed on all processors, but with a fixed time skew maintained between the instruction execution times on the separate processors.The fundamental concept is illustrated by the simple example of 'rig. 1. In this example, the second order direct form filter of Fig. la is implemented by a single processor program as shown in ig. 2b. In this single processor realization, none of the delay elements are realized directly, but rather the output from each delay element becomes an input to the program and the input to each delay element becomes an output of the program. In the SSIMD realization, these delayed values are not computed by this processor, but are supplied from identical computations on other processors. Fig. 2 shows a diagram of a one processor, a two processor, and a five processor SSIMD realization for the signal flow graph of Fig. 1. In the single processor solution of Fig. 2a, all of the past values of r(n) are supplied by the same processor, and there is never an issue of data availability. In the two processor realization of Fig. 2b, alternate points are supplied by each processor, and the two processors must be skewed such that the data requirements of each is always met by the ...

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“…(1) the design is very modular, reducing the complexity of the switching logic by a factor of four; (2) During the row transforms, each processor module works with data paths from each of the memory modules, for example, processor module 1 will be working with data paths D0 and Dl from each of the memory modules; processor module 2 will be working with data paths D2 and D3 from every memory module and so on. The processor modules have four data paths coming in and eight going out.…”

Section: The 2d-fft Processormentioning

confidence: 99%

A video rate two dimensional FFT processor

Joshi

McDonald²,

Steinvorth³

ICASSP '80. IEEE International Conference on Acoustics, Speech, and Signal Processing

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This paper describes a parallel high speed multiprocessor architecture suitable for realizing a 5l2x5l2 point 2-D FFT in under 1/30 of a second; enabling real time video display processing. The hardware employs a constant geometry algorithm for the implementation and utilizes 16 butterfly processors. The machine can be described as a Multiple Instruction Multiple Data (MIMD) type of machine since 16 processors will be working on 16 sets of data simultaneously. The memory orqanization is modular in design and provides conflict-free access to all 16 processors at all times. The memory can be interfaced to a host computer which can do other nonreal time picture processing operations on the transformed image.

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Efficient implementation of one and two dimensional digital signal processing algorithms on a multi-processor architecture

Cited by 3 publications

References 1 publication

The implementation of an all digital speech synthesizer using a multimicroprocessor architecture

The implementation of an all digital speech synthesizer using a multimicroprocessor architecture

Optimum implementation of single time index signal flow graphs on synceronous multiprocessor machines

A video rate two dimensional FFT processor

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