1995
DOI: 10.1109/34.368153
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Efficient image processing algorithms on the scan line array processor

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Cited by 17 publications
(6 citation statements)
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“…The first part performs the calculation of y from the original image, which is described by equation (5). The second part takes y and the original image to form the enhanced image, as described by equations (1) and (3). In order to increase the processing speed, the datapath is segmented into stages and interlaced by registers to store intermediate results.…”
Section: Filter Design Considerationsmentioning
confidence: 99%
See 1 more Smart Citation
“…The first part performs the calculation of y from the original image, which is described by equation (5). The second part takes y and the original image to form the enhanced image, as described by equations (1) and (3). In order to increase the processing speed, the datapath is segmented into stages and interlaced by registers to store intermediate results.…”
Section: Filter Design Considerationsmentioning
confidence: 99%
“…The pixels in the modified-gradient image Dx [. ], are computed from y½m, n after normalization and multiplication by x[m, n] using equation (3).…”
Section: Qfum Operation Descriptionmentioning
confidence: 99%
“…As shown in Figure 5, the core of the system is a dedicated SIMD cellular architecture based on a linear array [18] of Q identical 1-bit Processing Elements …”
Section: Special Purpose Systemmentioning
confidence: 99%
“…Among them SPA seems to provide a best match to the 2-D structure of an image. However, previous studies [18][13] [6] [15] have shown that LPA has no less computational and data I/O efficiency than SPA when the number of PE is the same, despite its cheapest hardware cost. Based on the above knowledges, and together based on the observation that a flexible memory architecture will facilitate the design of parallelizing techniques, we have chosen a most straightforward memory and processor linear array architecture, where each PE is attached with a considerable amount of locally addressable memory and connected in a ring, as our underlying architecture.…”
Section: Parallelizing Technique Designmentioning
confidence: 99%