An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems

Kyo, Shorin; Okazaki, Shinichiro; Arai, Tamio

doi:10.1145/1080695.1069982

Cited by 22 publications

(16 citation statements)

References 28 publications

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“…Its type and number of operators -from 4 to 128 -can be customized at the time of chip design. For the automotive market, NEC has devised the ImapCar processor (Kyo, 2005) containing 128 SIMD -Single Instruction Multiple Data means that every processor executes the same instruction on different data, for example each processor do the same job on each pixel of an image -parallel arithmetic and logic units with a power consumption of more than one Watt. Xetal also proposes a programmable, massively-parallel processor integrating 320 computing units (Abbo, 2008).…”

Section: Programmable Architecturesmentioning

confidence: 99%

A Future for Integrated Diagnostic Helping

Thévenin¹,

Kolar²

2011

Health Management - Different Approaches and Solutions

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Section: Programmable Architecturesmentioning

confidence: 99%

A Future for Integrated Diagnostic Helping

Thévenin¹,

Kolar²

2011

Health Management - Different Approaches and Solutions

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“…Parallelizing methods are designed based on the idea of sweeping PUL in various ways across the 2-D memory plane [7]. As described in the previous subsection, the one RAM/block per PE configuration enables each PE to access a different memory address at the same time, thus enabling sweeping of the PUL in various ways across the 2-D memory plane.…”

Section: Programming Modelmentioning

confidence: 99%

“…The performance of major image processing tasks and vision applications implemented on IMAPCAR by using several standard parallelizing techniques [7] are evaluated by comparing 1DC code running on a 100 MHz IMAPCAR with C code running on a 2.4 GHz Intel P4, a GPP (general purpose processor). As shown in Figure 11, the first benchmark, which consists of various image processing tasks, IMAPCAR achieves a performance up to 8 times better with a speedup approximately proportional to the amount of inherent parallelism of each task.…”

Section: Performance and Power Consumption Evaluationmentioning

confidence: 99%

IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements

Kyo

Okazaki

2008

J Sign Process Syst

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This paper presents IMAPCAR, a 100GOPS programmable highly parallel vision processor LSI consuming less than 2 W of power for in-vehicle vision tasks of driver assistance systems. First, requirements of vision processors for driver assistance systems as well as the characteristics of vision tasks for safety are summarized. Next, features in the design of IMAPCAR are described in detail, which comparing with a previous design, improved the performance for major vision tasks by a factor of 2.5 while reduced 50% of power. Design choices taken by other in-vehicle vision processors are also compared and analyzed. Finally, technology perspectives of future invehicle vision processors are discussed.

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“…By avoiding cache coherence overheads as well as cache indeterminacy, the shared L2 TCDM can be used as a frame buffer for video processing which should deal with a large amount of data within a tightly bounded time [7,8]. The fully combinational Mesh-of-Trees (MoT) interconnection network proposed in [5] is suitable for this shared multi-banked L2 TCDM with high throughput and low memory access latency.…”

Section: Introductionmentioning

confidence: 99%

A high-throughput and low-latency interconnection network for multi-core Clusters with 3-D stacked L2 tightly-coupled data memory

Kang

Benini

Micheli

2012

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)

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Abstract-The performance of most digital systems today is limited by the interconnect latency between logic and memory, rather than by the performance of logic or memory itself. Threedimensional (3-D) integration using through-silicon-vias (TSVs) may provide a solution to overcome the scaling limitations by stacking multiple memory dies on top of a many-core die. In this paper, we propose a Mesh-of-Trees (MoT) network to support high-throughput and low-latency communication between processing cores and 3-D stacked multi-banked shared L2 data memory. Compared to conventional MoT network [5] that is straightforwardly adapted to 3-D integration, the experimental results show that the proposed network significantly improves the number of operations per second. We also investigate the architecture parameters of 3-D memory stacking (e.g., number of tiers to be stacked, TSV sharing, etc.) that affect the interconnection network as well as the system performance and fabrication cost, which permits to explore trade-offs among different 3-D memory stacking architectures.

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An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems

Abstract: Embedded processors for video image recognition require to address both the cost (

Cited by 22 publications

References 28 publications

A Future for Integrated Diagnostic Helping

A Future for Integrated Diagnostic Helping

IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements

A high-throughput and low-latency interconnection network for multi-core Clusters with 3-D stacked L2 tightly-coupled data memory

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