Efficient identification of hot data for flash memory storage systems

Hsieh, Jen-Wei; Kuo, Tei-Wei; Chang, Li-Pin

doi:10.1145/1138041.1138043

Cited by 164 publications

(75 citation statements)

References 5 publications

(8 reference statements)

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…In addition, performance improvement through hot and cold data classification is also a typical performance improvement technique [13], [14]. Various policies for hot and cold data separation have also been proposed [1], [2]. Meanwhile, Kim et al propose a buffer management scheme called BPLRU to mitigate GC cost induced by random writes [3].…”

Section: Background and Related Workmentioning

confidence: 99%

“…Performance of the flash storage device is greatly influenced by the efficiency of cleaning operations. In order to minimize cleaning cost, many researches such as hot/cold data classification policies [1], [2] and buffer management policy [3] through pattern analysis of I/O requests have been conducted. However, it is difficult to obtain sufficient performance improvement of storage devices without help of the host system, with only limited information in the storage device.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Analysis of Performance for NAND Flash Based SSDs via Using Host Semantic Information

Kim

Park

2017

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYThe use of flash memory based storage devices is rapidly increasing, and user demands for high performance are also constantly increasing. The performance of the flash storage device is greatly influenced by cleaning operations of Flash Translation Layer (FTL). Various studies have been conducted to lower the cost of cleaning operations. However, there are limits to achieve sufficient performance improvement of flash storages without help of a host system, with only limited information in storage devices. Recently, SCSI, eMMC, and UFS standards provide an interface for sending semantic information from a host system to a storage device.In this paper, we analyze effects of semantic information on performance and lifetime of flash storage devices. We evaluate performance and lifetime improvement through SA-FTL (Semantic Aware Flash Translation Layer), which can take advantage of semantic information in storage devices. Experiments show that SA-FTL improves performance and lifetime of flash based storages by up to 30 and 35%, respectively, compared to a simple page-level FTL.

show abstract

Section: Background and Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analysis of Performance for NAND Flash Based SSDs via Using Host Semantic Information

Kim

Park

2017

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

show abstract

“…For capturing frequency, unlike other existing hot data detection schemes, our proposed scheme does not maintain a specific counter for all LBAs; instead, the number of BF can present its frequency information so that it consumes a very small amount of memory (8KB) which corresponds to a half of the state-of-the-art scheme [20]. Recency (as well as the frequency) is another important factor to identify hot data.…”

Section: Addressing Mode Switchesmentioning

confidence: 99%

“…Hot and cold data identification itself, however, is out of scope of this paper. Different algorithms such as the LRU discipline [21], sampling-based approach [22], or multihash function scheme [20] can also substitute for our approach.…”

Section: Addressing Mode Switchesmentioning

confidence: 99%

“…Converting all cold data that have not been referenced for a long time to the block-level mapping wastes a memory space for the mapping table and pays an expensive read/write cost to collect them. This is based on the fact that generally only a small fraction of the address space for a disk is frequently referenced [20]. When they are frequently accessed in a read manner, CFTL converts this type of cold data blocks to a block-level mapping.…”

Section: Addressing Mode Switchesmentioning

confidence: 99%

See 1 more Smart Citation

A Dynamic Switching Flash Translation Layer Based on Page-Level Mapping

Park

Debnath

2016

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYThe Flash Translation Layer (FTL) is a firmware layer inside NAND flash memory that allows existing disk-based applications to use it without any significant modifications. Since the FTL has a critical impact on the performance and reliability of flash-based storage, a variety of FTLs have been proposed. The existing FTLs, however, are designed to perform well for either a read intensive workload or a write intensive workload, not for both due to their internal address mapping schemes. To overcome this limitation, we propose a novel hybrid FTL scheme named Convertible Flash Translation Layer (CFTL). CFTL is adaptive to data access patterns with the help of our unique hot data identification design that adopts multiple bloom filters. Thus, CFTL can dynamically switch its mapping scheme to either page-level mapping or block-level mapping to fully exploit the benefits of both schemes. In addition, we design a spatial locality-aware caching mechanism and adaptive cache partitioning to further improve CFTL performance. Consequently, both the adaptive switching scheme and the judicious caching mechanism empower CFTL to achieve good read and write performance. Our extensive evaluations demonstrate that CFTL outperforms existing FTLs. In particular, our specially designed caching mechanism remarkably improves the cache hit ratio, by an average of 2.4×, and achieves much higher hit ratios (up to 8.4×) especially for random read intensive workloads.

show abstract

A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory–based SSDs

Alsalibi

Mittal

Al-Betar

et al. 2018

Concurrency and Computation

View full text Add to dashboard Cite

Flash memory-based solid-state drives (SSDs) offer several attractive features and benefits compared to hard disk drive (HDD), such as shock resistance and better performance especially for random data access. Depending on the number of bits in each cell, Flash memory can be designed as single/multi/triple level cell (SLC/MLC/TLC), which have different performance, density, cost and write endurance characteristics. To bring the best of these together, several researchers have proposed designing SSD using hybrid SLC/MLC/TLC Flash memory. However, these SSDs also present several challenges such as buffer management, placement of hot/cold data in suitable portion, and intelligent garbage collection. Several recent techniques aim to address these challenges.In this paper, we present a survey of techniques for managing SSDs designed with SLC/MLC/TLC Flash memory. We classify the works on several axes to bring out their similarities and differences.We aim to synthesize the state-of-art progress in hybrid SSD management and also spark further research in this area. KEYWORDSflash translation layer, garbage collection, hybrid solid state disk, NAND flash memory, wear leveling INTRODUCTIONAs the amount of digital data continues to grow at an exponential rate and key applications become more data intensive, efficient storage architectures and management techniques have become more important than ever before. Conventionally, hard disk drive* has been used as a storage device; however, its limitations such as poor performance (especially for random accesses), higher form factor, and vulnerability to shocks and magnetic fields have encouraged researchers to explore its alternatives.Flash memory is a promising technology for designing storage devices due to its several attractive properties, eg, high performance and density, low power consumption, noise-free operation, and immunity to shocks and magnetic fields. 2-6 Also, its cost has been decreasing in recent years and it is expected to provide even better cost efficiency than HDD in near future. Based on the number of bits stored in each cell, Flash can be characterized as SLC (1 bit), MLC † (2 bit) and TLC (3 bits). As shown in Table 1, these cell types provide a spectrum of properties and trade-offs. Specifically, on going from SLC to MLC to TLC, the performance and write endurance decrease whereas density and cost efficiency improve.To achieve the best of these three cell types, hybrid SSD designs have been proposed, which use Flash memories of multiple cell types to improve performance, energy efficiency, and reliability. 16 However, these hybrid SSD designs also bring challenges, such as selection of relative proportion of SLC/MLC/TLC, efficient mapping/moving of hot/cold data to them, accounting for their disparate write endurance and density values, and

show abstract

Efficient identification of hot data for flash memory storage systems

Cited by 164 publications

References 5 publications

Analysis of Performance for NAND Flash Based SSDs via Using Host Semantic Information

Analysis of Performance for NAND Flash Based SSDs via Using Host Semantic Information

A Dynamic Switching Flash Translation Layer Based on Page-Level Mapping

A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory–based SSDs

Contact Info

Product

Resources

About