Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

Abstract

a b s t r a c tWe present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The highthroughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several MAP decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed parallel Turbo decoder has been synthesized, placed and routed in a 65-nm CMOS technology with a core area of 8.3 mm 2 and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 MAP decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations &

A novel QPP interleaver for parallel turbo decoder

“…For P =64, Our PAG consumes 4%, 24.4% and 27.8% area cost (9.2 % on average) and 4.4%, 28.6% and 22.2% power cost (9.8 % on average) respectively, as compared to [1,2,3]. The hardware cost of Sun's [1] work increases sharply with the growth of P. Ilnseher's [2] and Wang's [3] work exhibit the similar trend, while the hardware cost of our PAG increases slowly. Because our PAG only needs generating 2dP /4 BIAs while the other PAGs require 2dP BIAs.…”

“…The QPP addresses f (x) can be generated in the forward and backward recursive directions [1] using Eq. (1)∼Eq.…”

“…However, our BIA generation method is different. The works in [1,2,3] generate P BIAs to control one DSN while our method only generates P /4 BIAs. In the rest of this section, we first prove that our DSN can be controlled only by P /4 BIAs in Theorem 1, then we formulate our forward and backward BIA generation method with d =1, 2, 4, .... in Theorem 2.…”

“…Sun [1] proposed an on-the-fly forward and backward recursive QPP Interleaving Address Generator (QPP-IAG). However, the QPP-IAG must be replicated multiple times.…”

Application of Fixed Point Turbo Decoding Algorithm for Throughput Enhancement of SISO Parallel Advanced LTE Turbo Decoders

“…The performance of the decoder can be improved by several algorithms like Viterbi, Shannon's, SISO and parallel decoding to improve the coding. These algorithms provide high complexity [15].…”