Efficient hardware design for the upsampling in the H.264/SVC scalable video coding extension

Silva, Thaísa Leal da; Susin, Altamiro; Bampi, Sérgio; Rediess, Fabiane; Agostini, Luciano

doi:10.1109/vlsisoc.2009.6041366

Cited by 2 publications

(5 citation statements)

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“…The architecture designed in this paper was synthesized for the same Altera Stratix IV used in [8], aiming to establish some comparisons between the frame-based solution presented in [8] and the macroblock-based solution implemented in this work.…”

Section: Synthesis Results and Comparisonsmentioning

confidence: 99%

“…Table IV compares the hardware resources use and performance indicators of the macroblock-level filtering architecture designed in this paper and those presented in [8], based on frame-level filtering. From this table it is possible to verify that the current architecture requires 25% less ALUTs and DLRs (Dedicated Logic Registers) and uses about two hundred times less memory bits than the frame-level filtering solution.…”

Section: Synthesis Results and Comparisonsmentioning

confidence: 99%

“…From this table it is possible to verify that the current architecture requires 25% less ALUTs and DLRs (Dedicated Logic Registers) and uses about two hundred times less memory bits than the frame-level filtering solution. This large difference occurs because the architecture presented in [8] needs to store an entire frame to perform the upsampling filtering while the architecture presented in this paper performs the filtering at a macroblock level, storing only a macroblock and two rows and columns around it to perform each filtering.…”

Section: Synthesis Results and Comparisonsmentioning

confidence: 99%

“…The complete designed architecture for the upsampling method is presented in Figure 3. Unlike the solution presented in [8] which was also designed in our group and processed an entire frame at once, the architecture proposed in this paper operates at macroblock-level. This processing mode has the advantage that, to process each macroblock, we only have to store the macroblock to be filtered and two rows and two columns of the neighboring macroblocks, instead of storing the whole frame.…”

Section: Upsampler Architecturementioning

confidence: 99%

“…The macroblock-level processing causes important gains in the number of needed memory elements. This modification implied in changes to the design presented in [8], particularly on the structures of the luminance and chrominance modules, with respect to the registers, memories and the control algorithm.…”

Section: Upsampler Architecturementioning

confidence: 99%

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A Novel Macroblock-Level Filtering Upsampling Architecture for H.264/AVC Scalable Extension

Silva

Cruz

Agostini

2020

JICS

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The scalable extension of the H.264/AVC standard, also called H.264/AVC SVC standard or simply SVC standard uses spatial upsampling in the spatial scalability modes. This work presents a novel upsampling architecture designed for operation at macroblock level and dyadic upsampling ratio with QVGA as the base layer resolution and VGA as the enhancement resolution.The adoption of a macroblock-level solution translates into a more efficient use of hardware resources with savings of approximately 25% in the number of ALUTs and DLRs and using about two hundred times less memory bits, when compared to previously published works. The designed architecture was synthesized targeting four FPGAs: Altera Cyclone III and Stratix IV and Xilinx Spartan 3E and Virtex 4. The best throughput was reached by the Xilinx Virtex 4 device, with a processing rate of 506 VGA frames per second. The worst result was reached by the Xilinx Spartan 3E FPGA, with 249 VGA frames per second. All target FPGAs surpasses the necessary throughput to decode VGA videos in real time. This very high throughput is important especially when low power applications are considered, since with low operation frequencies (9.34MHz) it is possible to reach real time (30 frames per second) for all target FPGAs.

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Section: Synthesis Results and Comparisonsmentioning

confidence: 99%

Section: Synthesis Results and Comparisonsmentioning

confidence: 99%

Section: Synthesis Results and Comparisonsmentioning

confidence: 99%

Section: Upsampler Architecturementioning

confidence: 99%

Section: Upsampler Architecturementioning

confidence: 99%

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