Efficient FPGA implementation of convolution

Mohammad, Khader; Agaian, Sos S.

doi:10.1109/icsmc.2009.5346737

Cited by 27 publications

(17 citation statements)

References 8 publications

(16 reference statements)

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“…For instance, all the algorithms presented in [3], [13], [15], [16], [18], [20] and [10] can be expressed in that form, as well as algorithms for scientific computation, such as convolution and the Jacobi iterative algorithm to solve linear eigenvalue problems [17].…”

Section: Target Family Of Algorithmsmentioning

confidence: 99%

Efficient Hardware Design of Iterative Stencil Loops

Rana

Beretta

Bruschi

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/).In case of abuse or copyright appearing without permission e-mail repository@westminster.ac.uk Abstract-A large number of algorithms for multidimensional signals processing and scientific computation come in the form of iterative stencil loops (ISLs), whose data dependencies span across multiple iterations. Because of their complex inner structure, automatic hardware acceleration of such algorithms is traditionally considered as a difficult task.In this paper, we introduce an automatic design flow that identifies, in a wide family of bidimensional data processing algorithms, sub-portions that exhibit a kind of parallelism close to that of ISLs; these are mapped onto a space of highly optimized ad-hoc architectures, which is efficiently explored to identify the best implementations with respect to both area and throughput. Experimental results show that the proposed methodology generates circuits whose performance is comparable to that of manually-optimized solutions, and orders of magnitude higher than those generated by commercial HLS tools.

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Section: Target Family Of Algorithmsmentioning

confidence: 99%

Efficient Hardware Design of Iterative Stencil Loops

Rana

Beretta

Bruschi

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…For instance, all the algorithms presented in [1], [2], [4], [8] and [11] can be expressed in that form. However, if the whole algorithm has to be repeated several times starting from different input data, as it happens in [4], each execution can be considered independent from the others, since they do not share intermediate results.…”

Section: Target Family Of Algorithmsmentioning

confidence: 99%

“…In the last years, embedded systems have become a valuable platform not only for simple and low-power applications, but also for the implementation of very complex algorithms, especially in the field of image and video processing [1]. Within this context, iterative algorithms that work on large matrices [11] can be implemented today on Graphics Processing Units (GPUs), Multi-Processor Systems-on-Chip (MPSoCs) or Field Programmable Gate Arrays (FPGAs).…”

Section: Introductionmentioning

confidence: 99%

Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms

et al. 2013

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Abstract-Traditionally, parallel implementations of multimedia algorithms are carried out manually, since the automation of this task is very difficult due to the complex dependencies that generally exist between different elements of the data set. Moreover, there is a wide family of iterative multimedia algorithms that cannot be executed with satisfactory performance on Multi-Processor Systems-on-Chip or Graphics Processing Units. For this reason, new methods to design custom hardware circuits that exploit the intrinsic parallelism of multimedia algorithms are needed.As a consequence, in this paper, we propose a novel design method for the definition of hardware systems optimized for a particular class of multimedia iterative algorithms. We have successfully applied the proposed approach to several realworld case studies, such as iterative convolution filters and the Chambolle algorithm, and the proposed design method has been able to automatically implement, for each one of them, a parallel architecture able to meet real-time performance (up to 72 frames per second for the Chambolle algorithm), with on-chip memory requirements from 2 to 3 orders of magnitude smaller than the state-of-the art approaches.

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“…In this case, the bus area was smaller, but the throughput of the bus was halved (since the frequency remained the same). In a deep submicron technology, the switching energy consumed due to coupling capacitance is dominant [16,17,[24][25][26]. The disadvantage of bus widening is that the bus occupies more area than a conventional bus.…”

Section: Bus Serialization and Wideningmentioning

confidence: 99%

On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding

2014

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In chip-multiprocessors (CMP) architecture, the L2 cache is shared by the L1 cache of each processor core, resulting in a high volume of diverse data transfer through the L1-L2 cache bus. High-performance CMP and SoC systems have a significant amount of data transfer between the on-chip L2 cache and the L3 cache of off-chip memory through the power expensive off-chip memory bus. This paper addresses the problem of the high-power consumption of the on-chip data buses, exploring a framework for memory data bus power consumption minimization approach. A comprehensive analysis of the existing bus power minimization approaches is provided based on the performance, power, and area overhead consideration. A novel approaches for reducing the power consumption for the on-chip bus is introduced. In particular, a serialization-widening (SW) of data bus with frequent value encoding (FVE), called the SWE approach, is proposed as the best power savings approach for the on-chip cache data bus. The experimental results show that the SWE approach with FVE can achieve approximately 54% power savings over the conventional bus for multicore applications using a 64-bit wide data bus in 45 nm technology.

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Efficient FPGA implementation of convolution

Cited by 27 publications

References 8 publications

Efficient Hardware Design of Iterative Stencil Loops

Efficient Hardware Design of Iterative Stencil Loops

Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms

On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding

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