Efficient FPGA implementation of AES 128 bit for IEEE 802.16e mobile WiMax standards

Abstract

In the present era of high speed communication, wireless technology plays a predominant role in data transmission. In the timeline of wireless domain, Wi-Fi, Bluetooth, ZigBee are some of the standards used in today's wireless medium. In addition, WiMax is introduced by IEEE as IEEE 802.16 standard for long distance communication, and mobile WiMax as 802.16e. WiMax is an acronym of worldwide interoperability for microwave access. It helps to provide wireless transmission with high quality of service in a secured environment. Privacy across the network and access control is the predominant goal in the wireless protocol. In the wireless environment one of the most widely used security algorithms in MAC layer is Advanced Encryption Standard (AES). Especially Medium Access Control (MAC) sub layer should be evaluated in the security architecture. AES is used in the MAC layer that consumes more power and involves high cost. So, in this paper an optimized architecture of AES 128 bit counter mode security algorithm for MAC layer of 802.16e standard is proposed. The SBOX and MixColumn transformation are modified in the architecture of AES to achieve optimized power and delay. The design has been implemented in Xilinx virtex5 device and power has been analyzed using XPower analyzer. It is compared with two standard existing architectures. The simulation results revealed a power reduction of 41% compared to existing one.

Real Time FPGA Implementation of a High Speed for Video Encryption and Decryption System with High Level Synthesis Tools

“…The research presents a comparative analysis and investigation into edge recognition filters implemented on Field-Programmable Gate Arrays (FPGAs) for real-time processing of video and images techniques [10]. Babu et al [11] present a succinct analysis of the various classifications of FPGA architecture and their corresponding applications.…”

“…Furthermore, this algorithm can be effectively implemented on both software and hardware platforms; AES software versions give poorer physical security but require fewer resources [8,9]. However, the increasing need for secure data transmissions at high speeds and volumes while maintaining physical security makes hardware implementation of the AES algorithm imperative [10,11]. The primary challenge with applications utilized in these domains is to ensure real-time system operation [2].…”

10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform

“…Before performing the post-implementation simulations of the whole system including encryption and decryption blocks, the behavioral simulations with 220 MHz clock frequency have been carried out. In Figure 21, the temporal trends of the signals are shown, obtained providing the plaintext data packets (red box) to the encryption/decryption system every 40.86 ns; this data-rate derives from the clock frequency of 220 MHz, corresponding to 4.54 ns clock period, chosen to comply with the 3 Gbit/s throughput required by the specifications of Wireless Connector system, as calculated below in Equation (5). The area utilization resulting from the post-implementation simulations remains unchanged compared to the results obtained through the post-synthesis simulations, showing, for the encryption system, resource utilization of 5% of LUTs, 1% of FFs, 1% of I/O ports and 1% of BUFGs, as well as for the decryption system, 10% of LUTs, 1% of FFs, 1% of I/O ports and 1% of BUFGs; finally, for both the system, there is a 25% area utilization relative to the IP Clocking Wizard block used to generate the system clock during the post-synthesis and post-implementation simulations.…”

“…Before performing the post-implementation simulations of the whole system including encryption and decryption blocks, the behavioral simulations with 220 MHz clock frequency have been carried out. In Figure 21, the temporal trends of the signals are shown, obtained providing the plaintext data packets (red box) to the encryption/decryption system every 40.86 ns; this data-rate derives from the clock frequency of 220 MHz, corresponding to 4.54 ns clock period, chosen to comply with the 3 Gbit/s throughput required by the specifications of Wireless Connector system, as calculated below in Equation (5). The encryption of the data packets is performed in 9.5 clock periods (white box); in fact, the encrypted packets are provided at the output of the encryption block on the falling edge of the clock, after exactly 9.5 clock periods and then acquired by the decryption block on the next rising edge.…”

A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

“…This large amount of information must be processed and shared in a very secure manner. Since information is treated as a most valuable thing, there is also a very high chance of piracy or alteration of this information by an unintended user [1][2][3][4][5]. Unauthorized change and availability of the original information also form the major goal of the researchers to keep the information secure.…”