10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform

Abstract

The security of communication and computer systems is an increasingly important issue, nowadays pervading all areas of human activity (e.g., credit cards, website encryption, medical data, etc.). Furthermore, the development of high-speed and light-weight implementations of the encryption algorithms is fundamental to improve and widespread their application in low-cost, low-power and portable systems. In this scientific article, a high-speed implementation of the AES-128 algorithm is reported, developed for a short-range and high-frequency communication system, called Wireless Connector; a Xilinx ZCU102 Field Programmable Gate Array (FPGA) platform represents the core of this communication system since manages all the base-band operations, including the encryption/decryption of the data packets. Specifically, a pipelined implementation of the Advanced Encryption Standard (AES) algorithm has been developed, allowing simultaneous processing of distinct rounds on multiple successive plaintext packets for each clock period and thus obtaining higher data throughput. The proposed encryption system supports 220 MHz maximum operating frequency, ensuring encryption and decryption times both equal to only 10 clock periods. Thanks to the pipelined approach and optimized solutions for the Substitute Bytes operation, the proposed implementation can process and provide the encrypted packets each clock period, thus obtaining a maximum data throughput higher than 28 Gbit/s. Also, the simulation results demonstrate that the proposed architecture is very efficient in using hardware resources, requiring only 1631 Configurable Logic Blocks (CLBs) for the encryption block and 3464 CLBs for the decryption one.

FPGA based technical solutions for high throughput data processing and encryption for 5G communication: A review

“…To compare the different solutions, the efficiency has been chosen as a merit figure since it considers the obtained throughput jointly and used hardware resources. From the results in Table 2, it is evident that the AES-128 implementation proposed in [16] supports a relatively high data throughput (up to 28.16 Gbit/s) but uses fewer hardware resources compared to other similar works reported in the literature; therefore, it obtains a higher value of efficiency. By comparing the proposed solution with those reported in [52], the first supports a higher data throughput (i.e.…”

“…As above described, in [16], we proposed a high-speed and resource-efficient implementation of the well known AES-128 encryption/decryption algorithm, developed for a custom high-frequency (around 60 GHz), short-range (1-10 m) communication system, named "wireless connector". A Xilinx ZCU102 development board has been employed as the core section of the developed communication apparatus, implementing all the baseband tasks, such as modulation/demodulation, coding/decoding, and encryption/decryption to ensure communication security.…”

“…Afterwards, innovative architectures of encryption/decryption algorithms designed by employing the Xilinx Zynq Ultrascale+ MPSoC ZCU102 platform are discussed. Furthermore, a high-speed and lightweight implementation of the AES-128 algorithm is introduced, properly developed for a high-frequency short-range communication apparatus, named "wireless connector" [16]. The Xilinx ZCU102 FPGA platform constitutes the main section of the "wireless connector" system, managing all the baseband tasks, including the encryption/decryption of the data packets [17].…”

“…Therefore, the paper is arranged as follows: in section 2 are presented the main FPGA devices' applications in 5G networks/systems, whereas, in section 3, the implementations of encryption/decryption algorithms by Xilinx Zynq Ultrascale+ MPSoC ZCU102 platform are described in the sub-section 3.1; the comparison of our high-speed and resource-efficient AES-128 encryption/decryption system [16] with other similar implementations is introduced in the sub-section 3.2. Finally, an overview of the main applications of FPGA devices, based on the Xilinx ZCU102 platform, for high-speed processing is reported in section 4.…”

Implementation of Speed-Efficient Key-Scheduling Process of AES for Secure Storage and Transmission of Data

“…Nowadays, the growth of lightweight, robust, and effective encryption algorithms are required to provide network security for information technology applications. The developed encryption algorithms are essential for maximizing the throughput and data size of IoT, and it is used in mobile transmissions, video streaming, real-time communications, and so on [1][2][3][4][5][6]. The methods of encryption/decryption are classified into two types such as symmetric and asymmetric methods.…”