Efficient FPGA Implementation Architecture of Fast FIR Algorithm Using Han-Carlson Adder Based Vedic Multiplier

Paliwal, Payal; Sharma, Janki Ballabh

doi:10.1109/icirca.2018.8597432

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Efficient FPGA Implementation Architecture of Fast FIR Algorithm Using Han-Carlson Adder Based Vedic Multiplier

Cited by 4 publications

References 9 publications

Comparative study of FFA architectures using different multiplier and adder topologies

Comparative study of FFA architectures using different multiplier and adder topologies

ASIC design of power and area efficient programmable FIR filter using optimized Urdhva-Tiryagbhyam Multiplier for impedance cardiography

VLSI implementation of vedic multiplier and carry look ahead adder based FIR filter for denoising EEG signal

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