Comparative study of FFA architectures using different multiplier and adder topologies

Paliwal, Payal; Sharma, Janki Ballabh; Nath, Vijay

doi:10.1007/s00542-019-04678-8

Cited by 13 publications

(2 citation statements)

References 13 publications

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“…However, the latter has lower power consumption and lower energy delay product (EDP). Similar comparisons are reported in Shanmuganathan and Brindhadevi 46 and Paliwal et al 47 …”

Section: Review Of Recent Literature On Hardware Implementation Of Fi...supporting

confidence: 89%

“…However, the latter has lower power consumption and lower energy delay product (EDP). Similar comparisons are reported in Shanmuganathan and Brindhadevi 46 and Paliwal et al 47 In Sumalatha et al, 33 low-pass filter architecture has been proposed for denoising of ECG signals. The core of the proposed architecture includes processing element (PE) which is a VM incorporating carry look-ahead adder (VM-CLA) and a control unit (CU).…”

Section: Review Of Recent Literature On Hardware Implementation Of Fi...supporting

confidence: 78%

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ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Janwadkar,

Dhavse

2023

Circuit Theory & Apps

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The design of hand‐held portable devices for cardiovascular health monitoring based on the analysis of electrocardiogram (ECG) is a hot topic of research nowadays. Digital filters, possibly designed using digital multipliers, are a critical module in the design of such analysis systems. This paper presents the ASIC design of a 64th‐order digital low‐pass FIR filter to be used in ECG denoising applications. The FIR filter is optimized for usage in battery‐operated portable systems, wherein power consumption and on‐chip area are crucial parameters of concern. These challenges are met by employing a novel multiplier architecture, which we design by hybridizing the two popular digital multiplication algorithms, namely, the Vedic multiplication algorithm and the Wallace tree multiplication algorithm. The proposed multiplier consumes lower area and power consumption than either of the aforementioned conventional multiplication algorithms. This is established through FPGA‐based implementations on Artix‐7 FPGA, for the various wordlengths. The area and power optimizations are further exercised by two proposed techniques, namely, elimination of redundant multipliers, and power gating using the proposed zero‐detector circuit. RTL‐to‐GDSII flow has been completed using Cadence digital design and sign‐off tools for SCL 180 nm technology. The results indicate that the proposed filter architecture occupies 16.38% lower area and 79.58% lower power consumption than the contemporary designs described in the literature.

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“…However, the latter has lower power consumption and lower energy delay product (EDP). Similar comparisons are reported in Shanmuganathan and Brindhadevi 46 and Paliwal et al 47 …”

Section: Review Of Recent Literature On Hardware Implementation Of Fi...supporting

confidence: 89%

Section: Review Of Recent Literature On Hardware Implementation Of Fi...supporting

confidence: 78%

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Janwadkar,

Dhavse

2023

Circuit Theory & Apps

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High Speed and Low Power Buffer Based Parallel Multiplier for Computer Arithmetic

Chakravarthy¹,

Vignesh²,

Swaminathan³

2020

Lecture Notes in Networks and Systems

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Low Area-High Speed Architecture of Efficient FIR Filter Using Look Ahead Clock Gating Technique

Devi¹,

Rajesh²,

LIKITHA³

et al. 2023

Advances in Cognitive Science and Communications

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Comparative study of FFA architectures using different multiplier and adder topologies

Cited by 13 publications

References 13 publications

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

High Speed and Low Power Buffer Based Parallel Multiplier for Computer Arithmetic

Low Area-High Speed Architecture of Efficient FIR Filter Using Look Ahead Clock Gating Technique

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