Efficient exception handling support for GPUs

Tanasic, Ivan; Gelado, Isaac; Jordà, Marc; Ayguadé, Eduard; Navarro, Nacho

doi:10.1145/3123939.3123950

Cited by 6 publications

(2 citation statements)

References 40 publications

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“…Today, machine checks [54] (e.g., ECC errors in the cache/memory hierarchy) are the only example of imprecise exception in modern CPUs because they are non-restartable and cause the OS to terminate the process or even crash. Finally, emerging accelerators such as GPUs [55] adopt imprecise exceptions because precise exceptions pose a dramatic performance overhead or require significantly more silicon area and power. As computing systems evolve, the cost of supporting precise exceptions and their programming implications are being gradually revisited with new constraints.…”

Section: Precise Exceptionsmentioning

confidence: 99%

Imprecise Store Exceptions

Gupta

Kang

et al. 2023

Proceedings of the 50th Annual International Symposium on Computer Architecture

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Precise exceptions are a cornerstone of modern computing as they provide the abstraction of sequential instruction execution to programmers while accommodating microarchitectural optimizations. However, increasing compute capabilities in deep memory hierarchies (e.g., software event handlers, programmable accelerators) expose long exception detection latencies that forgo precise exception semantics for retired stores awaiting completion. Unfortunately, well-known post-retirement speculation mechanisms to tolerate these latencies require excessively large microarchitectural structures per core. This paper rethinks the role of architecture and OS in supporting precise exceptions. We show that instead of forcing the architecture to support precise exceptions transparently in all cases, it is preferable to employ hardware-software co-design to handle imprecise store exceptions efficiently. We develop formalism to prove that this approach complies with underlying memory consistency models and design a RISC-V prototype that passes all litmus tests, demonstrating its efficacy. CCS CONCEPTS• Computer systems organization → Architectures.

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Section: Precise Exceptionsmentioning

confidence: 99%

Imprecise Store Exceptions

Gupta

Kang

et al. 2023

Proceedings of the 50th Annual International Symposium on Computer Architecture

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“…To handle page fault, Power et al [11] gave one hardware solution, which modified CPU interrupt return microcode and added one extra CPU register to handle GPU page fault. But extra hardware support is not necessary, Tanasic et al [14] gave 3 possible design of GPU page handler (Wrap Disabling, Replay Queue or Operand log), which could remove CPU involvement in GPU page fault.…”

Section: Rit Note That This Communication Is Batched Each Communicamentioning

confidence: 99%

Statistical caching for near memory management

Chen

Liu

Mingyang

et al. 2019

Proceedings of the International Symposium on Memory Systems

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Modern GPUs often use near memory or high-bandwidth memory, which may be managed as cache when the application data is too large to fit in the near memory. Unlike CPU caches, the near memory cache has a much larger size. A recent approach is statistical caching, which shows near optimal results when managing large memory for file caching. The prior work is ideal and not practical. This paper outlines two extensions. It first formulates a new caching algorithm called least expected use (LEU) replacement and shows, through examples, that the statistical solution automatically integrates two otherwise disparate policies. Then the paper describes a system design to implement LEU. To position the new design for discussion, the paper draws parallels with two familiar ideas, branch prediction and spectral analysis, and considers a set of opportunities and challenges of achieving statistical caching in near memory. CCS CONCEPTS • Computer systems organization → Heterogeneous (hybrid) systems; • Software and its engineering → Memory management.

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Bypass-Enabled Thread Compaction for Divergent Control Flow in Graphics Processing Units

Jiang

Guo

et al. 2020

J. Shanghai Jiaotong Univ. (Sci.)

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Efficient exception handling support for GPUs

Cited by 6 publications

References 40 publications

Imprecise Store Exceptions

Imprecise Store Exceptions

Statistical caching for near memory management

Bypass-Enabled Thread Compaction for Divergent Control Flow in Graphics Processing Units

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